Re: analog layout

I think you need to figure out what your logical grid is.

Then you need to map your starting technology to your target
technology.

Then you need to map each starting technology rule to an equivalent
target technology rule.
This step will likely be filled with inconsistencies.

The starting technology will have a physical grid of some dimension.
The target technology may have a different physical grid.

One solution is to scale a copy of your structures into the target
technology.

Then you need to adjust each rule/structure to fit into the new
technology
This step is filled with tradeoffs as you will have cases where the
target technology has larger or smaller constraints that
the starting technology. Sometime the solution here is to accept the
larger of the two. Other times you need to modify the
structure. Simple devices, interconnect. contacts can be mapped fairly
quickly. Complex structures may require complex rewrites.

Once you have mapped into a few of each style of
device/technology/structure then the process can become almost
automated,
but special cases seem to come up.

I found that somestructures were tricky. I/O structures often do not
scale with the rest of the process as some of the physics of them
require constant size.
Sensitive analog circuits are also problematic as some noise issues do
not scale well.

Straight CMOS and voltage devices ( Resistors, Capacitors) scale ok,
but Bipolars and Current sensitive devices are usually somewhat
non-linear and require some sophisticated tuning to get close to the
right kind of translation.

I have had considerable success in mapping CMOS logic from 0.5u -> 0.4u
-> 0.3u -> 0.25u -> .18u -> .15u -> 0.13u ... 90nm AND 65nm were
problematic due to DFM requirements.

Some bipolar circuits can be scaled in a limited way, but require very
careful checking that the ccts. are still close to their optimal
operational ranges.

YMMV

-- Gerry

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