comp.cad.cadence

• Date Index

• using analog artist to simulate a certian MC run?, Sam
• Analog Layout Training, Roland.Fontaine@xxxxxxxxx
  • Re: Analog Layout Training, Bernd Fischer
  • Re: Analog Layout Training, DReynolds
• VXL: Setting Contact xBias/yBias, Edward Dodge
  • Re: VXL: Setting Contact xBias/yBias, Bernd Fischer
• Mutli-Level Logic To 2-Level Logic Conversion, hamidrezah
• Who also designs in AMIS0.5u using the adsArtist + Virtuoso & Calibre, decertan
• disk space for spectreS simulations, desai . vandana
  • Re: disk space for spectreS simulations, Bernd Fischer
    • Re: disk space for spectreS simulations, desai . vandana
  • Re: disk space for spectreS simulations, Andrew Beckett
• How to add or customize Schematic Pins?, drc_98
  • Re: How to add or customize Schematic Pins?, sunkey.zheng@xxxxxxxxx
  • Re: How to add or customize Schematic Pins?, Andrew Beckett
• two professional technology forums, water9580
• Assura and floating pins, rickm
  • Re: Assura and floating pins, TimRoy1
• how to customize open configuration form?, Bernd Fischer
  • Re: how to customize open configuration form?, Andrew Beckett
  • Re: how to customize open configuration form?, fogh
• Calling a function inside a Viewfile Window ?, mohanr
  • Re: Calling a function inside a Viewfile Window ?, Andrew Beckett
• Paths ending with 90 Degree bend less than 1/2 width long problem, TimRoy1
  • Re: Paths ending with 90 Degree bend less than 1/2 width long problem, Frank E. Gennari
    • Re: Paths ending with 90 Degree bend less than 1/2 width long problem, TimRoy1
• Buggy behaviour with Analog DE / Spectre and newline in input.scs, decertan
  • Re: Buggy behaviour with Analog DE / Spectre and newline in input.scs, fogh
    • Re: Buggy behaviour with Analog DE / Spectre and newline in input.scs, Andrew Beckett
• Is there any easy way or SKILL program to put VIA arrays correctly on the diagonal path ?, sunkey . zheng
• getting the list of cellviews in hierarchy, Rajeswaran M
  • Re: getting the list of cellviews in hierarchy, Andrew Beckett
• version control using subversion, stroller
  • Re: version control using subversion, John Gianni
    • Re: version control using subversion, fogh
      • Re: version control using subversion, jbrand
      • Re: version control using subversion, Svenn Are Bjerkem
      • Re: version control using subversion, fogh
• dump pcell code, camelot
  • Re: dump pcell code, Jimka
    • Re: dump pcell code, camelot
      • Re: dump pcell code, jbrand
      • Re: dump pcell code, Andrew Beckett
• NCVHDL code coverage analysis:doubt, srj
• how to setup interface between cadence design frame work and hspice, ponderboy
  • Re: how to setup interface between cadence design frame work and hspice, Andrew Beckett
• How to toggle how an item is mirrored in virtuoso layout, tstengerster@xxxxxxxxx
  • Re: How to toggle how an item is mirrored in virtuoso layout, Dominic Duvarney
• how to run a full spice netlist not the subcircuit in the spectre, samanta . susovon
  • Re: how to run a full spice netlist not the subcircuit in the spectre, Andrew Beckett
    • Re: how to run a full spice netlist not the subcircuit in the spectre, fogh
• Simulating Noise in SC voltage amplifier, reactgary
• ncelab's problem, battlefield2001
• 'icfb' versus 'seultra'/'sedsm', hamidrezah
  • Re: 'icfb' versus 'seultra'/'sedsm', John Gianni
  • Re: 'icfb' versus 'seultra'/'sedsm', Singu
• Reminder: CDNLive! Silicon Valley 2006 - Call for Papers, Michael Catrambone
• Schematics for ISCAS89 benchmarks, Fazela
  • Re: Schematics for ISCAS89 benchmarks, hamidrezah
• Cadence SimVision TCL signal probing, lookfwd
• spice netlist 2 schematic (cadence composer), Rajeswaran M
  • Re: spice netlist 2 schematic (cadence composer), Bernd Fischer
    • Re: spice netlist 2 schematic (cadence composer), Andrew Beckett
      • Re: spice netlist 2 schematic (cadence composer), John Gianni
• PSL and ncsim, rick.richmond@xxxxxxxxxxxx
• Pin names not used when extracting layout --> spice netlist, decertan
  • Re: Pin names not used when extracting layout --> spice netlist, S.Badel
    • Re: Pin names not used when extracting layout --> spice netlist, decertan
• Display instance name in layout view, jbrand
  • Re: Display instance name in layout view, S. Badel
    • Re: Display instance name in layout view, jbrand
      • Re: Display instance name in layout view, jbrand
• Trouble with laplace_zp, Stefan Joeres
  • Re: Trouble with laplace_zp, Prasanna
  • Re: Trouble with laplace_zp, Andrew Beckett
    • Re: Trouble with laplace_zp, Steve
      • Re: Trouble with laplace_zp, Andrew Beckett
• PHASE NOISE Analysis in Spectre, michael_skoufis
  • Re: PHASE NOISE Analysis in Spectre, Thomas Ussmueller
    • Re: PHASE NOISE Analysis in Spectre, michael_skoufis
• Cadence Help Needed, CADDUDE
• neocell CellArch, mekhail
  • Re: neocell CellArch, mxn731
• override predefined model parameter?, cyseok
  • Re: override predefined model parameter?, JD
  • Re: override predefined model parameter?, Andrew Beckett
• pcell error, SS
  • Re: pcell error, jbrand
• probing a net in schematic, kamal
  • <Possible follow-ups>
  • probing a net in schematic, kamal
• stack overflow with skill routine, stroller
• hassle of cover page, comp.cad.cadence
  • Re: hassle of cover page, Svenn Are Bjerkem
  • Re: hassle of cover page, Bernd Fischer
    • Re: hassle of cover page, comp.cad.cadence
      • Re: hassle of cover page, fogh
    • Re: hassle of cover page, Svenn Are Bjerkem
      • Re: hassle of cover page, fogh
      • Re: hassle of cover page, Svenn Are Bjerkem
• using enterPoint with infix turned on, SS
  • Re: using enterPoint with infix turned on, Dominic Duvarney
    • Re: using enterPoint with infix turned on, SS
    • Re: using enterPoint with infix turned on, SS
• RCX extraction problem in assura, neo
  • Re: RCX extraction problem in assura, Andrew Beckett
• object oriented SKILL, Jimka
  • Re: object oriented SKILL, Andrew Beckett
• SKILL: Post-process Symbol Pins, Bernd Fischer
  • Re: SKILL: Post-process Symbol Pins, Andrew Beckett
    • Re: SKILL: Post-process Symbol Pins, Bernd Fischer
• Job Opening in Munich for Lisp Programmer, Jimka
• Force analog design environment to use one stimulus file, decertan
  • Re: Force analog design environment to use one stimulus file, Bernd Fischer
    • Re: Force analog design environment to use one stimulus file, decertan
      • Re: Force analog design environment to use one stimulus file, Svenn Are Bjerkem
      • Re: Force analog design environment to use one stimulus file, decertan
      • Re: Force analog design environment to use one stimulus file, Bernd Fischer
      • Re: Force analog design environment to use one stimulus file, decertan
      • Re: Force analog design environment to use one stimulus file, Andrew Beckett
• Re: calibre drc, jainmanish123
• how to remove a variable in SKILL, kamal
  • Re: how to remove a variable in SKILL, Bernd Fischer
    • Re: how to remove a variable in SKILL, Bernd Fischer
      • Re: how to remove a variable in SKILL, kamal
  • Re: how to remove a variable in SKILL, Jimka
    • Re: how to remove a variable in SKILL, Bernd Fischer
      • Re: how to remove a variable in SKILL, Jimka
  • Re: how to remove a variable in SKILL, Jimka
    • Re: how to remove a variable in SKILL, kamal
• Pointers in Skill?, Rajeswaran M
  • Re: Pointers in Skill?, Jimka
    • Re: Pointers in Skill?, fogh
      • Re: Pointers in Skill?, Jimka
      • Re: Pointers in Skill?, Rajeswaran M
• AMIS C5 process with cadence, neo
  • Re: AMIS C5 process with cadence, decertan
    • Re: AMIS C5 process with cadence, neo
      • Re: AMIS C5 process with cadence, decertan
• licensing a skill app, stroller
• How to remove a metal layer '("M2" "D0") recursively in a top level block (layout), davidncw
  • Re: How to remove a metal layer '("M2" "D0") recursively in a top level block (layout), Jimka
    • Re: How to remove a metal layer '("M2" "D0") recursively in a top level block (layout), davidncw
      • Re: How to remove a metal layer '("M2" "D0") recursively in a top level block (layout), Jimka
      • Re: How to remove a metal layer '("M2" "D0") recursively in a top level block (layout), davidncw
• Re: Auto-generating schematics using SKILL, John Gianni
• cdb vs OA, tritue
  • Re: cdb vs OA, Bernd Fischer
    • Re: cdb vs OA, Svenn Are Bjerkem
      • Re: cdb vs OA, tritue
      • Re: cdb vs OA, fogh
• Can't plot phase noise from pnoise result window in SpectreRF, Zhiheng Cao
  • Re: Can't plot phase noise from pnoise result window in SpectreRF, Andrew Beckett
• function to remove duplicate elements from list ?, Jimka
  • Re: function to remove duplicate elements from list ?, nicolasperrier
    • Re: function to remove duplicate elements from list ?, Andrew Beckett
      • Re: function to remove duplicate elements from list ?, Dominic Duvarney
      • Re: function to remove duplicate elements from list ?, Dominic Duvarney
      • Re: function to remove duplicate elements from list ?, John Gianni
      • Re: function to remove duplicate elements from list ?, fogh
      • Re: function to remove duplicate elements from list ?, Dominic Duvarney
• wont simulate, DJ
• How to save the results calculated in OCEAN?, cyseok
  • Re: How to save the results calculated in OCEAN?, fogh
• Problem about reducing series resistors for LVS in Dracula, nige
• Re, Hrishikesh
• a professional bus community and resource, ted
• Extra routing room by suppressing pads, brian
  • Re: Extra routing room by suppressing pads, daytripper
• hey help me out please, chandras
  • Re: hey help me out please, Andrew Beckett
• any projects on CADENCE please, aj
  • Re: any projects on CADENCE please, Jimka
    • Re: any projects on CADENCE please, aj
      • Re: any projects on CADENCE please, John Gianni
• default behaviour for double click onto views within library manager, Frank Nitsche
  • Re: default behaviour for double click onto views within library manager, Dominic Duvarney
  • Re: default behaviour for double click onto views within library manager, Andrew Beckett
  • Re: default behaviour for double click onto views within library manager, Frank Nitsche
• Re: off grid DRC in layout xl, jainmanish123
• Sell high quality HDI PCB (CHINA), njsldz@xxxxxxx
  • Re: Sell high quality HDI PCB (CHINA), njsldz@xxxxxxx
• Re: Figure Causing Multiple Stamped Connections, vdvalk@xxxxxxxxxx
  • Re: Figure Causing Multiple Stamped Connections, chunling . lau
    • Re: Figure Causing Multiple Stamped Connections, Edward Kalenda
• Re: custom keyboard macros, vdvalk@xxxxxxxxxx
• Problem with floor, Pradeep Kumar Chawda
  • Re: Problem with floor, Andrew Beckett
  • Re: Problem with floor, Jimka
• skill compiler, Jimka
  • Re: skill compiler, Edward Kalenda
    • Re: skill compiler, Jimka
      • Re: skill compiler, Edward Kalenda
      • Re: skill compiler, Jimka
      • Re: skill compiler, spambaitster
      • Re: skill compiler, Jimka
      • Re: skill compiler, Svenn Are Bjerkem
      • Re: skill compiler, Jimka
• current through inherited connections, chava
  • Re: current through inherited connections, John Gianni
    • Re: current through inherited connections, John Gianni
  • Re: current through inherited connections, Andrew Beckett
• RC xtraction, chandras
  • Re: RC xtraction, vdvalk@xxxxxxxxxx
• "ignore case option" for rex commands, Rajeswaran M
  • Re: "ignore case option" for rex commands, Dominic Duvarney
    • Re: "ignore case option" for rex commands, Rajeswaran M
      • Re: "ignore case option" for rex commands, Dominic Duvarney
      • Re: "ignore case option" for rex commands, Andrew Beckett
• Schematic porting, Hrishikesh
  • Re: Schematic porting, DReynolds
  • Re: Schematic porting, Jimka
  • Re: Schematic porting, Jimka
    • Re: Schematic porting, DReynolds
      • Re: Schematic porting, Hrishikesh
  • Re: Schematic porting, anderson_tw
    • Re: Schematic porting, Hrishikesh
      • Re: Schematic porting, DReynolds
      • Re: Schematic porting, Hrishikesh
      • Re: Schematic porting, DReynolds
      • Re: Schematic porting, Hrishikesh
      • Re: Schematic porting, tstengerster@xxxxxxxxx
• regarding PLL noise analysis, us1710
  • Re: regarding PLL noise analysis, John Gianni
• Netname expansion, any cadence public function?, Rajeswaran M
  • Re: Netname expansion, any cadence public function?, Dominic DuVarney
    • Re: Netname expansion, any cadence public function?, Andrew Beckett
      • Re: Netname expansion, any cadence public function?, Dominic DuVarney
      • Re: Netname expansion, any cadence public function?, Rajeswaran M
• DRC fix capability, llc
  • Re: DRC fix capability, Andrew Beckett
    • Re: DRC fix capability, John Gianni
  • Re: DRC fix capability, vdvalk@xxxxxxxxxx
• Re: How to count instances in a hierarchy, Kholdoun TORKI
  • <Possible follow-ups>
  • Re: How to count instances in a hierarchy, Dominic Duvarney
    • Re: How to count instances in a hierarchy, TimRoy1
      • Re: How to count instances in a hierarchy, Dominic Duvarney
      • Re: How to count instances in a hierarchy, TimRoy1
  • Re: How to count instances in a hierarchy, Jimka
• logarithmic step for ocnPrint() function?, stephen . greenwood
  • Re: logarithmic step for ocnPrint() function?, Andrew Beckett
    • Re: logarithmic step for ocnPrint() function?, stephen . greenwood
• Re: IBM_PDK Banner doesn't stay in Layout XL editor, fogh
• Re: howto get a list of all (locally) defined variables, John Gianni
  • Re: howto get a list of all (locally) defined variables, Jimka
• Problems saving and plotting branch currents with HSPICE - bug?, ShamShoon
• Re: PCell layers, Andrew Beckett
  • Re: PCell layers, Jimka
    • Re: PCell layers, Andrew Beckett
• Re: property bags and pcells, Andrew Beckett
  • Re: property bags and pcells, SS
  • <Possible follow-ups>
  • Re: property bags and pcells, fogh
• Re: compiled SKILL scripts, Andrew Beckett

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