comp.cad.cadence

• Thread Index

---

• Re: How to count instances in a hierarchy
  • From: llc
• Re: How to count instances in a hierarchy
  • From: llc
• property bags and pcells
  • From: SS
• compiled SKILL scripts
  • From: Roland.Fontaine@xxxxxxxxx
• Re: IBM_PDK Banner doesn't stay in Layout XL editor
  • From: Roland.Fontaine@xxxxxxxxx
• Re: PCell layers
  • From: TimRoy1
• off grid DRC in layout xl
  • From: Daniel Firu
• PCell layers
  • From: jbxvt
• Re: how tp generate a LEF?
  • From: fogh
• Re: ipcBeginProcess
  • From: fogh
• Re: IBM_PDK Banner doesn't stay in Layout XL editor
  • From: fogh
• Re: get view found by design->hierarchy->descend
  • From: fogh
• Re: Auto-generating schematics using SKILL
  • From: DReynolds
• Re: Generating Template from command line
  • From: SS
• Re: howto get a list of all (locally) defined variables
  • From: Andrew Beckett
• Re: Odd Problem in Schematic Editor
  • From: Andrew Beckett
• IBM_PDK Banner doesn't stay in Layout XL editor
  • From: mxkdirs
• Re: howto get a list of all (locally) defined variables
  • From: Erik Wanta
• Re: nport and layout LVS
  • From: Erik Wanta
• Re: Odd Problem in Schematic Editor
  • From: mxkdirs
• Re: Generating Template from command line
  • From: Andrew Beckett
• Re: Odd Problem in Schematic Editor
  • From: Andrew Beckett
• Re: howto get a list of all (locally) defined variables
  • From: Andrew Beckett
• Re: nport and layout LVS
  • From: Andrew Beckett
• how tp generate a LEF?
  • From: ponderboy
• Re: CADENCE & Solaris x86
  • From: PM
• Generating Template from command line
  • From: SS
• Re: get view found by design->hierarchy->descend
  • From: Erik Wanta
• howto get a list of all (locally) defined variables
  • From: paul
• Odd Problem in Schematic Editor
  • From: mxkdirs
• Re: get view found by design->hierarchy->descend
  • From: fogh
• Re: CADENCE & Solaris x86
  • From: Edward Kalenda
• Re: nport and layout LVS
  • From: mxkdirs
• Re: nport and layout LVS
  • From: mxkdirs
• Re: common-centroid using Layout XL
  • From: Erik Wanta
• Re: about AMS modeling in Cadence
  • From: Erik Wanta
• Re: Simulating a varactor in spectre
  • From: Erik Wanta
• Re: Installation on IC5141base and update
  • From: Erik Wanta
• Re: nport and layout LVS
  • From: Erik Wanta
• Re: ipcBeginProcess
  • From: S. Badel
• Re: CADENCE & Solaris x86
  • From: PM
• Re: How to master SKILL language ?
  • From: Pete nospam Zakel
• nport and layout LVS
  • From: mxkdirs
• nport and layout LVS
  • From: mxkdirs
• Installation on IC5141base and update
  • From: eda_cadence
• get view found by design->hierarchy->descend
  • From: Erik Wanta
• Re: How to master SKILL language ?
  • From: Junhua Mao
• Re: CADENCE & Solaris x86
  • From: Junhua Mao
• Re: Auto-generating schematics using SKILL
  • From: NigelD
• Re: Auto-generating schematics using SKILL
  • From: Bernd Fischer
• Re: Auto-generating schematics using SKILL
  • From: NigelD
• ipcBeginProcess
  • From: Roland.Fontaine@xxxxxxxxx
• Re: copy and changing properties
  • From: SS
• Re: Basic Question: Setting variables at runtime
  • From: S.Badel
• Modifying rodRectangles properties
  • From: Suresh Jeevanandam
• Re: Auto-generating schematics using SKILL
  • From: Andrew Beckett
• Re: Auto-generating schematics using SKILL
  • From: John Gianni
• Auto-generating schematics using SKILL
  • From: NigelD
• Re: Basic Question: Setting variables at runtime
  • From: ShamShoon
• Re: LVS problems with Assura
  • From: Bea
• Re: copy and changing properties
  • From: tstengerster@xxxxxxxxx
• Re: ansLvsCompPrim netlisting procedure for auLvs
  • From: Andrew Beckett
• Re: LVS problems with Assura
  • From: Andrew Beckett
• Re: Query regarding to read and simulate the spice netlist in Cadence Spectre
  • From: Andrew Beckett
• Re: Basic Question: Setting variables at runtime
  • From: S. Badel
• Re: SKILL Q: How the get the viewType?
  • From: Suresh Jeevanandam
• copy and changing properties
  • From: SS
• Converting a SPICE model to a .dml file in SpecctraQuest SI
  • From: jc_webs
• Converting a SPICE model to a .dml file in SpecctraQuest SI
  • From: jc_webs
• Compilation order of verilog files in NCVerilog/VCS simulator to choose the dealy mode
  • From: kesava . talupuru
• Re: ansLvsCompPrim netlisting procedure for auLvs
  • From: anandganesan@xxxxxxxxx
• Query regarding to read and simulate the spice netlist in Cadence Spectre
  • From: samanta . susovon
• Re: SKILL Q: How the get the viewType?
  • From: tstengerster@xxxxxxxxx
• Basic Question: Setting variables at runtime
  • From: ShamShoon
• SKILL Q: How the get the viewType?
  • From: Bernd Fischer
• Re: LNA gain calculation in Spectre
  • From: Andrew Beckett
• Re: Problems with ncsim and ams simulation
  • From: Andrew Beckett
• Re: Simulating a varactor in spectre
  • From: Andrew Beckett
• Re: input-referred port noise
  • From: Andrew Beckett
• Re: How to count instances in a hierarchy
  • From: Andrew Beckett
• LVS problems with Assura
  • From: Bea
• Re: Problems with ncsim and ams simulation
  • From: Andreas
• Re: Problems with ncsim and ams simulation
  • From: Prasanna
• PA Simulation in SpectreRF
  • From: mxkdirs
• input-referred port noise
  • From: Jack
• Simulating a varactor in spectre
  • From: Maz
• How to count instances in a hierarchy
  • From: spectrallypure
• LNA gain calculation in Spectre
  • From: Maz
• What is the common strategy to do RF simulation and measurement with pads?
  • From: Frank
• Transmission Line in Cadence
  • From: mxkdirs
• Re: How to run monte carlo using spectreS
  • From: Andrew Beckett
• Re: How to run monte carlo using spectreS
  • From: Zhiheng Cao
• Re: Cadence virtouso layout and Mentor calibre DRC
  • From: Kholdoun TORKI
• Problems with ncsim and ams simulation
  • From: Andreas
• Re: Cadence virtouso layout and Mentor calibre DRC
  • From: suresh
• Re: Cadence virtouso layout and Mentor calibre DRC
  • From: suresh
• Re: How to define a user defined function in AEL
  • From: Andrew Beckett
• Re: How to run monte carlo using spectreS
  • From: Andrew Beckett
• Re: Figure Causing Multiple Stamped Connections
  • From: cAddIE
• How to define a user defined function in AEL
  • From: Zhiheng Cao
• How to run monte carlo using spectreS
  • From: Zhiheng Cao
• Re: Creating HSPICE netlist without primitives cell subcircuits
  • From: ShamShoon
• Re: Cadence virtouso layout and Mentor calibre DRC
  • From: Kholdoun TORKI
• Re: Cadence virtouso layout and Mentor calibre DRC
  • From: tstengerster@xxxxxxxxx
• about AMS modeling in Cadence
  • From: Eric
• Re: Characterizing the pll
  • From: John Gianni
• Re: Creating HSPICE netlist without primitives cell subcircuits
  • From: Andrew Beckett
• Re: specifying default symbolic contact
  • From: Andrew Beckett
• Re: Creating HSPICE netlist without primitives cell subcircuits
  • From: ShamShoon
• Re: specifying default symbolic contact
  • From: danmc
• Re: calibre drc
  • From: Bernd Fischer
• calibre drc
  • From: Roland.Fontaine@xxxxxxxxx
• Re: Creating HSPICE netlist without primitives cell subcircuits
  • From: fogh
• Re: ansLvsCompPrim netlisting procedure for auLvs
  • From: Bernd Fischer
• Re: ansLvsCompPrim netlisting procedure for auLvs
  • From: Andrew Beckett
• Cadence virtouso layout and Mentor calibre DRC
  • From: suresh
• Re: specifying default symbolic contact
  • From: Andrew Beckett
• Re: Figure Causing Multiple Stamped Connections
  • From: Andrew Beckett
• Re: ansLvsCompPrim netlisting procedure for auLvs
  • From: Bernd Fischer
• Re: Creating HSPICE netlist without primitives cell subcircuits
  • From: Andrew Beckett
• Figure Causing Multiple Stamped Connections
  • From: Balavelan
• Re: Creating HSPICE netlist without primitives cell subcircuits
  • From: mk
• Creating HSPICE netlist without primitives cell subcircuits
  • From: ShamShoon
• Re: Characterizing the pll
  • From: John Gianni
• Re: Characterizing the pll
  • From: Andrew Beckett
• Re: visual diff with numeric field and tolerance (for comparing netlists)
  • From: Andrew Beckett
• Re: Using a new standard cell library with Synopsys Design Analyser
  • From: Fazela
• Using a new standard cell library with Synopsys Design Analyser
  • From: Fazela
• ansLvsCompPrim netlisting procedure for auLvs
  • From: anandganesan@xxxxxxxxx
• Re: xoomsys (just trying my luck)
  • From: fogh
• Re: visual diff with numeric field and tolerance (for comparing netlists)
  • From: fogh
• Re: specifying default symbolic contact
  • From: danmc
• specifying default symbolic contact
  • From: danmc
• Re: Characterizing the pll
  • From: nagendra
• Re: visual diff with numeric field and tolerance (for comparing netlists)
  • From: grigsoft
• Re: visual diff with numeric field and tolerance (for comparing netlists)
  • From: grigsoft
• Re: Characterizing the pll
  • From: John Gianni
• Re: dump instance CDF
  • From: John Gianni
• Re: Characterizing the pll
  • From: John Gianni
• Re: segmentation fault big split bus
  • From: Dominic Duvarney
• Characterizing the pll
  • From: nagendra
• Cadence DFM Tool
  • From: llc
• Re: xoomsys (just trying my luck)
  • From: tstengerster@xxxxxxxxx
• Re: order of signals in ncsim waveform window
  • From: Michael Laajanen
• Re: visual diff with numeric field and tolerance (for comparing netlists)
  • From: Andrew Beckett
• Re: order of signals in ncsim waveform window
  • From: anupam
• visual diff with numeric field and tolerance (for comparing netlists)
  • From: fogh
• NC-Sim Questions
  • From: mottoblatto
• Please help for "Objectives" on VLM
  • From: sen
• Re: order of signals in ncsim waveform window
  • From: Michael Laajanen
• segmentation fault big split bus
  • From: Emanuele . Mandelli
• Re: DIVA error after upgrade to lastest USR
  • From: tritue
• Re: multi-part path
  • From: Bernd Fischer
• Re: common-centroid using Layout XL
  • From: TimRoy1
• Re: multi-part path
  • From: ajd
• Re: multi-part path
  • From: Bernd Fischer
• multi-part path
  • From: ajd
• Re: order of signals in ncsim waveform window
  • From: anupam
• Re: DIVA error after upgrade to lastest USR
  • From: Edward Kalenda
• common-centroid using Layout XL
  • From: arslanumut
• DIVA error after upgrade to lastest USR
  • From: tritue
• Re: window trigger needed
  • From: Dominic Duvarney
• Re: Shrink/Magnify Symbols
  • From: SS
• Re: window trigger needed
  • From: Andrew Beckett
• Re: window trigger needed
  • From: Pete nospam Zakel
• Spectre Convergence problem (Dynamic Comparator)
  • From: katyal
• Re: VXL change layer for adding paths and rectangles
  • From: TimRoy1
• Re: corners analysis woes
  • From: danmc
• Re: Specctraquest
  • From: Michael Laajanen
• Re: ASSURA - dummy problem
  • From: jayl-news
• Re: VXL change layer for adding paths and rectangles
  • From: Andrew Beckett
• Re: Shrink/Magnify Symbols
  • From: Andrew Beckett
• Re: window trigger needed
  • From: Dominic Duvarney
• VXL change layer for adding paths and rectangles
  • From: TimRoy1
• Re: window trigger needed
  • From: Andrew Beckett
• Re: Shrink/Magnify Symbols
  • From: SS
• Re: window trigger needed
  • From: Bernd Fischer
• Re: window trigger needed
  • From: Dominic Duvarney
• Re: window trigger needed
  • From: Bernd Fischer
• Re: window trigger needed
  • From: Dominic DuVarney
• Re: Shrink/Magnify Symbols
  • From: Andrew Beckett
• Re: corners analysis woes
  • From: Andrew Beckett
• Re: window trigger needed
  • From: Andrew Beckett
• where to look for layout contractors?
  • From: lchian
• Re: ASSURA - dummy problem
  • From: Bernd Fischer
• Re: Shrink/Magnify Symbols
  • From: SS
• xoomsys (just trying my luck)
  • From: fogh
• Re: Shrink/Magnify Symbols
  • From: fogh
• Shrink/Magnify Symbols
  • From: SS
• corners analysis woes
  • From: danmc
• Re: window trigger needed
  • From: Dominic Duvarney
• window trigger needed
  • From: Dominic Duvarney
• ASSURA - dummy problem
  • From: Stefan Bormann
• Re: custom keyboard macros
  • From: Andrew Beckett
• ISVLSI 2006 - Call for Participation
  • From: ISVLSI 2006
• Re: custom keyboard macros
  • From: vdvalk@xxxxxxxxxx
• Re: order of signals in ncsim waveform window
  • From: Michael Laajanen
• Re: skill pcell example
  • From: shankar.cds@xxxxxxxxxxxxxx
• order of signals in ncsim waveform window
  • From: meanupam
• Re: skill pcell example
  • From: boriswart
• Re: skill pcell example
  • From: xiaolong
• Re: DRC Verification Problem
  • From: Fazela
• Specctraquest
  • From: Michael Laajanen
• ISVLSI 2006 - Call for Participation
  • From: ISVLSI 2006
• Re: Annotating Operating Point in Cadence
  • From: Bernd Fischer
• Re: ICFB
  • From: Johannes Grad
• Re: RTL-Compiler [read in the Netlist]
  • From: ldm
• ICFB
  • From: dutchman1234@xxxxxxxxxxx
• Re: Encounter: rdaInit.tcl failed
  • From: Johannes Grad
• Annotating Operating Point in Cadence
  • From: ajay . balan
• How to calculate phase noise?
  • From: KK
• Re: DRC Verification Problem
  • From: Johannes Grad
• Re: Plotting osillation frequency vs. current
  • From: Andrew Beckett
• Re: RTL-Compiler [read in the Netlist]
  • From: Paulbill
• Plotting osillation frequency vs. current
  • From: Vitaliy
• Re: Show hidden files in cadence file browsers
  • From: fogh
• Re: Show hidden files in cadence file browsers
  • From: Andrew Beckett
• Re: weird formInitProc error?
  • From: Raj
• Re: dump instance CDF
  • From: fogh
• Re: Show hidden files in cadence file browsers
  • From: Andrew Beckett
• Re: Show hidden files in cadence file browsers
  • From: fogh

We are proud to have Web Hosting and Rack Housing from 9 Net Avenue Deutschland.
(18)