comp.cad.cadence

• Date Index

• property bags and pcells, SS
• compiled SKILL scripts, Roland.Fontaine@xxxxxxxxx
• off grid DRC in layout xl, Daniel Firu
• PCell layers, jbxvt
  • Re: PCell layers, TimRoy1
• IBM_PDK Banner doesn't stay in Layout XL editor, mxkdirs
  • Re: IBM_PDK Banner doesn't stay in Layout XL editor, fogh
    • Re: IBM_PDK Banner doesn't stay in Layout XL editor, Roland.Fontaine@xxxxxxxxx
• how tp generate a LEF?, ponderboy
  • Re: how tp generate a LEF?, fogh
• Generating Template from command line, SS
  • Re: Generating Template from command line, Andrew Beckett
    • Re: Generating Template from command line, SS
• howto get a list of all (locally) defined variables, paul
  • Re: howto get a list of all (locally) defined variables, Andrew Beckett
    • Re: howto get a list of all (locally) defined variables, Erik Wanta
      • Re: howto get a list of all (locally) defined variables, Andrew Beckett
• Odd Problem in Schematic Editor, mxkdirs
  • Re: Odd Problem in Schematic Editor, Andrew Beckett
    • Re: Odd Problem in Schematic Editor, mxkdirs
      • Re: Odd Problem in Schematic Editor, Andrew Beckett
• nport and layout LVS, mxkdirs
  • Re: nport and layout LVS, Erik Wanta
    • Re: nport and layout LVS, mxkdirs
      • Re: nport and layout LVS, mxkdirs
      • Re: nport and layout LVS, Andrew Beckett
      • Re: nport and layout LVS, Erik Wanta
  • <Possible follow-ups>
  • nport and layout LVS, mxkdirs
• Installation on IC5141base and update, eda_cadence
  • Re: Installation on IC5141base and update, Erik Wanta
• get view found by design->hierarchy->descend, Erik Wanta
  • Re: get view found by design->hierarchy->descend, fogh
    • Re: get view found by design->hierarchy->descend, Erik Wanta
      • Re: get view found by design->hierarchy->descend, fogh
• Re: How to master SKILL language ?, Junhua Mao
  • Re: How to master SKILL language ?, Pete nospam Zakel
• Re: CADENCE & Solaris x86, Junhua Mao
  • Re: CADENCE & Solaris x86, PM
    • Re: CADENCE & Solaris x86, Edward Kalenda
      • Re: CADENCE & Solaris x86, PM
• ipcBeginProcess, Roland.Fontaine@xxxxxxxxx
  • Re: ipcBeginProcess, S. Badel
    • Re: ipcBeginProcess, fogh
• Modifying rodRectangles properties, Suresh Jeevanandam
• Auto-generating schematics using SKILL, NigelD
  • Re: Auto-generating schematics using SKILL, John Gianni
    • Re: Auto-generating schematics using SKILL, NigelD
      • Re: Auto-generating schematics using SKILL, Bernd Fischer
      • Re: Auto-generating schematics using SKILL, NigelD
      • Re: Auto-generating schematics using SKILL, DReynolds
  • Re: Auto-generating schematics using SKILL, Andrew Beckett
• copy and changing properties, SS
  • Re: copy and changing properties, tstengerster@xxxxxxxxx
    • Re: copy and changing properties, SS
• Converting a SPICE model to a .dml file in SpecctraQuest SI, jc_webs
  • <Possible follow-ups>
  • Converting a SPICE model to a .dml file in SpecctraQuest SI, jc_webs
• Compilation order of verilog files in NCVerilog/VCS simulator to choose the dealy mode, kesava . talupuru
• Query regarding to read and simulate the spice netlist in Cadence Spectre, samanta . susovon
  • Re: Query regarding to read and simulate the spice netlist in Cadence Spectre, Andrew Beckett
• Basic Question: Setting variables at runtime, ShamShoon
  • Re: Basic Question: Setting variables at runtime, S. Badel
    • Re: Basic Question: Setting variables at runtime, ShamShoon
      • Re: Basic Question: Setting variables at runtime, S.Badel
• SKILL Q: How the get the viewType?, Bernd Fischer
  • Re: SKILL Q: How the get the viewType?, tstengerster@xxxxxxxxx
  • Re: SKILL Q: How the get the viewType?, Suresh Jeevanandam
• LVS problems with Assura, Bea
  • Re: LVS problems with Assura, Andrew Beckett
    • Re: LVS problems with Assura, Bea
• PA Simulation in SpectreRF, mxkdirs
• input-referred port noise, Jack
  • Re: input-referred port noise, Andrew Beckett
• Simulating a varactor in spectre, Maz
  • Re: Simulating a varactor in spectre, Andrew Beckett
    • Re: Simulating a varactor in spectre, Erik Wanta
• How to count instances in a hierarchy, spectrallypure
  • Re: How to count instances in a hierarchy, Andrew Beckett
    • Re: How to count instances in a hierarchy, llc
    • Re: How to count instances in a hierarchy, llc
• LNA gain calculation in Spectre, Maz
  • Re: LNA gain calculation in Spectre, Andrew Beckett
• What is the common strategy to do RF simulation and measurement with pads?, Frank
• Transmission Line in Cadence, mxkdirs
• Problems with ncsim and ams simulation, Andreas
  • Re: Problems with ncsim and ams simulation, Prasanna
    • Re: Problems with ncsim and ams simulation, Andreas
      • Re: Problems with ncsim and ams simulation, Andrew Beckett
• How to define a user defined function in AEL, Zhiheng Cao
  • Re: How to define a user defined function in AEL, Andrew Beckett
• How to run monte carlo using spectreS, Zhiheng Cao
  • Re: How to run monte carlo using spectreS, Andrew Beckett
    • Re: How to run monte carlo using spectreS, Zhiheng Cao
      • Re: How to run monte carlo using spectreS, Andrew Beckett
• about AMS modeling in Cadence, Eric
  • Re: about AMS modeling in Cadence, Erik Wanta
• calibre drc, Roland.Fontaine@xxxxxxxxx
  • Re: calibre drc, Bernd Fischer
• Cadence virtouso layout and Mentor calibre DRC, suresh
  • Re: Cadence virtouso layout and Mentor calibre DRC, tstengerster@xxxxxxxxx
    • Re: Cadence virtouso layout and Mentor calibre DRC, suresh
  • Re: Cadence virtouso layout and Mentor calibre DRC, Kholdoun TORKI
    • Re: Cadence virtouso layout and Mentor calibre DRC, suresh
      • Re: Cadence virtouso layout and Mentor calibre DRC, Kholdoun TORKI
• Figure Causing Multiple Stamped Connections, Balavelan
  • Re: Figure Causing Multiple Stamped Connections, Andrew Beckett
    • Re: Figure Causing Multiple Stamped Connections, cAddIE
• Creating HSPICE netlist without primitives cell subcircuits, ShamShoon
  • Re: Creating HSPICE netlist without primitives cell subcircuits, mk
  • Re: Creating HSPICE netlist without primitives cell subcircuits, Andrew Beckett
    • Re: Creating HSPICE netlist without primitives cell subcircuits, fogh
      • Re: Creating HSPICE netlist without primitives cell subcircuits, Andrew Beckett
      • Re: Creating HSPICE netlist without primitives cell subcircuits, ShamShoon
    • Re: Creating HSPICE netlist without primitives cell subcircuits, ShamShoon
• Using a new standard cell library with Synopsys Design Analyser, Fazela
  • Re: Using a new standard cell library with Synopsys Design Analyser, Fazela
• ansLvsCompPrim netlisting procedure for auLvs, anandganesan@xxxxxxxxx
  • Re: ansLvsCompPrim netlisting procedure for auLvs, Bernd Fischer
    • Re: ansLvsCompPrim netlisting procedure for auLvs, Andrew Beckett
      • Re: ansLvsCompPrim netlisting procedure for auLvs, anandganesan@xxxxxxxxx
      • Re: ansLvsCompPrim netlisting procedure for auLvs, Andrew Beckett
    • Re: ansLvsCompPrim netlisting procedure for auLvs, Bernd Fischer
• specifying default symbolic contact, danmc
  • Re: specifying default symbolic contact, danmc
    • Re: specifying default symbolic contact, Andrew Beckett
      • Re: specifying default symbolic contact, danmc
      • Re: specifying default symbolic contact, Andrew Beckett
• Characterizing the pll, nagendra
  • Re: Characterizing the pll, John Gianni
    • Re: Characterizing the pll, John Gianni
    • Re: Characterizing the pll, nagendra
      • Re: Characterizing the pll, Andrew Beckett
      • Re: Characterizing the pll, John Gianni
      • Re: Characterizing the pll, John Gianni
• Cadence DFM Tool, llc
• visual diff with numeric field and tolerance (for comparing netlists), fogh
  • Re: visual diff with numeric field and tolerance (for comparing netlists), Andrew Beckett
    • Re: visual diff with numeric field and tolerance (for comparing netlists), fogh
      • Re: visual diff with numeric field and tolerance (for comparing netlists), Andrew Beckett
  • Re: visual diff with numeric field and tolerance (for comparing netlists), grigsoft
  • Re: visual diff with numeric field and tolerance (for comparing netlists), grigsoft
• NC-Sim Questions, mottoblatto
• Please help for "Objectives" on VLM, sen
• segmentation fault big split bus, Emanuele . Mandelli
  • Re: segmentation fault big split bus, Dominic Duvarney
• multi-part path, ajd
  • Re: multi-part path, Bernd Fischer
    • Re: multi-part path, ajd
      • Re: multi-part path, Bernd Fischer
• common-centroid using Layout XL, arslanumut
  • Re: common-centroid using Layout XL, TimRoy1
    • Re: common-centroid using Layout XL, Erik Wanta
• DIVA error after upgrade to lastest USR, tritue
  • Re: DIVA error after upgrade to lastest USR, Edward Kalenda
    • Re: DIVA error after upgrade to lastest USR, tritue
• Spectre Convergence problem (Dynamic Comparator), katyal
• VXL change layer for adding paths and rectangles, TimRoy1
  • Re: VXL change layer for adding paths and rectangles, Andrew Beckett
    • Re: VXL change layer for adding paths and rectangles, TimRoy1
• where to look for layout contractors?, lchian
• xoomsys (just trying my luck), fogh
  • Re: xoomsys (just trying my luck), tstengerster@xxxxxxxxx
    • Re: xoomsys (just trying my luck), fogh
• Shrink/Magnify Symbols, SS
  • Re: Shrink/Magnify Symbols, fogh
    • Re: Shrink/Magnify Symbols, SS
      • Re: Shrink/Magnify Symbols, Andrew Beckett
      • Re: Shrink/Magnify Symbols, SS
      • Re: Shrink/Magnify Symbols, Andrew Beckett
      • Re: Shrink/Magnify Symbols, SS
• corners analysis woes, danmc
  • Re: corners analysis woes, Andrew Beckett
    • Re: corners analysis woes, danmc
• window trigger needed, Dominic Duvarney
  • Re: window trigger needed, Dominic Duvarney
    • Re: window trigger needed, Andrew Beckett
  • Re: window trigger needed, Dominic DuVarney
    • Re: window trigger needed, Bernd Fischer
      • Re: window trigger needed, Dominic Duvarney
      • Re: window trigger needed, Bernd Fischer
      • Re: window trigger needed, Andrew Beckett
      • Re: window trigger needed, Dominic Duvarney
      • Re: window trigger needed, Andrew Beckett
      • Re: window trigger needed, Pete nospam Zakel
      • Re: window trigger needed, Dominic Duvarney
• ASSURA - dummy problem, Stefan Bormann
  • Re: ASSURA - dummy problem, Bernd Fischer
  • Re: ASSURA - dummy problem, jayl-news
• Re: custom keyboard macros, vdvalk@xxxxxxxxxx
  • Re: custom keyboard macros, Andrew Beckett
• order of signals in ncsim waveform window, meanupam
  • Re: order of signals in ncsim waveform window, Michael Laajanen
    • Re: order of signals in ncsim waveform window, anupam
      • Re: order of signals in ncsim waveform window, Michael Laajanen
      • Re: order of signals in ncsim waveform window, anupam
      • Re: order of signals in ncsim waveform window, Michael Laajanen
• Re: skill pcell example, xiaolong
  • Re: skill pcell example, boriswart
    • Re: skill pcell example, shankar.cds@xxxxxxxxxxxxxx
• Specctraquest, Michael Laajanen
  • Re: Specctraquest, Michael Laajanen
• ISVLSI 2006 - Call for Participation, ISVLSI 2006
  • <Possible follow-ups>
  • ISVLSI 2006 - Call for Participation, ISVLSI 2006
• ICFB, dutchman1234@xxxxxxxxxxx
  • Re: ICFB, Johannes Grad
• Re: Encounter: rdaInit.tcl failed, Johannes Grad
• Annotating Operating Point in Cadence, ajay . balan
  • Re: Annotating Operating Point in Cadence, Bernd Fischer
• How to calculate phase noise?, KK
• Re: DRC Verification Problem, Johannes Grad
  • Re: DRC Verification Problem, Fazela
• Re: RTL-Compiler [read in the Netlist], Paulbill
  • Re: RTL-Compiler [read in the Netlist], ldm
• Plotting osillation frequency vs. current, Vitaliy
  • Re: Plotting osillation frequency vs. current, Andrew Beckett
• Re: weird formInitProc error?, Raj
• Re: dump instance CDF, fogh
  • Re: dump instance CDF, John Gianni
• Re: Show hidden files in cadence file browsers, fogh
  • Re: Show hidden files in cadence file browsers, Andrew Beckett
    • Re: Show hidden files in cadence file browsers, fogh
  • <Possible follow-ups>
  • Re: Show hidden files in cadence file browsers, Andrew Beckett

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