calculating a config word during operating point analysis

Hi,

I have been trying to get the following problem solved using SpectreHDL
(but also reading in the Verilog-A manual):

How can I generate a config word during the dc operating point analysis
using AHDL or Verilog-A?

I want to simulate a calibration compensation for temperature and
process of an internal resistor which varies quite a lot. The resulting
word is used to switch on and off enough parallell transistors to get
the approximate value. (Running loads of montecarlo runs on different
temperatures)

I have an unclocked successive approximation circuit which manage to
find a 4-bit word during "dc" simulation, (that is during the "ic" run
in a transient simulation). This circuitry is quite heavy and it take
some time to generate that word, but it take even longer time in to find
the word during transient sim.

I have studied the manuals to understand that spectre perform one "ic"
cycle at the beginning to find the initial conditions before going on
doing transient. I have done something like:

module nada (anin anref dout) ()
analog {
if ($analysis("ic")) {
while (compare < reference) {
compare = V(anin);
reference = V(anref);
... convert ii to out[7:0] ...
ii++;
}
}
V(dout[7]) <- $transition(out[7], ... );
....
V(dout[0]) <- $transition(out[0], ... );
}

Beware that there are no variables declared and some lines missing.

My problem is that everything inside the while() loop is not getting out
of the code because I do not reach the V(dout..) lines at the bottom.

A second problem is that the $transition() function seems to stay stuck
at its initial value and not follow the upcount in the while() loop,
even if I move the $transition() statements into the while() loop. (I
can see in the debugger that it steps into the V() assignments without
anything happening on the output pins.

I have the fear that it is not possible to use a high level description
to solve this problem.

Hope for some help,
--
Svenn
.

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