comp.cad.cadence

Thread Index

spectres simulation with netlist file
- From: neo
Re: symbol + schematic pcells
- From: Trevor Bowen
Re: Does anybody use foundry PDK for production chip design?
- From: Trevor Bowen
Re: is there a way to delete global variables?
- From: Trevor Bowen
remane signals in SST2 database
- From: Prabhat Gupta
Re: is there a way to delete global variables?
- From: Andrew Beckett
Re: symbol + schematic pcells
- From: Andrew Beckett
spectre data not saved for schematic pcell
- From: Trevor Bowen
Re: symbol + schematic pcells
- From: Trevor Bowen
Re: is there a way to delete global variables?
- From: Trevor Bowen
Re: Does anybody use foundry PDK for production chip design?
- From: Trevor Bowen
Re: is there a way to delete global variables?
- From: Andrew Beckett
Re: how to use awd to view spectre command line simulation results
- From: Andrew Beckett
is there a way to delete global variables?
- From: bennys
Re: Labels in Virtuoso
- From: S. Badel
Re: how to use awd to view spectre command line simulation results
- From: Allen
Re: *Error* unknown: dbSetq: Can not set attribute
- From: saby
Re: calculating a config word during operating point analysis
- From: Andrew Beckett
Re: ocnPrint() problem in spectre
- From: Andrew Beckett
Re: Why the size of mos's w & l checked is wrong when I run lvs check using dracula?
- From: Andrew Beckett
Re: how to use awd to view spectre command line simulation results
- From: Andrew Beckett
Re: Weird errors, anybody know what sclSetAttribute is/does?
- From: Andrew Beckett
Re: *Error* unknown: dbSetq: Can not set attribute
- From: Andrew Beckett
Re: why I can not run assura
- From: jayl-news
Re: why I can not run assura
- From: Yifei Luo
Re: Importing DEF file in Cadence DFII
- From: fogh
Re: Does anybody use foundry PDK for production chip design?
- From: fogh
Re: How to make the output of spectre as text format in a file
- From: fogh
Read Hspice.tr0 file
- From: wolfchild02
Re: XL update source via lxiSetConnRef()
- From: paul
Re: Help: AC Analysis
- From: sheldonbrand
neocell constraint
- From: okguy
Re: Labels in Virtuoso
- From: trisha.woods
Re: symbol + schematic pcells
- From: S. Badel
SignalStorm: Help on warning "illegal instance is found"
- From: kristof
Re: symbol + schematic pcells
- From: S. Badel
Re: Help! Bus notation on schematics
- From: Bernd Fischer
Re: Labels in Virtuoso
- From: Bernd Fischer
*Error* unknown: dbSetq: Can not set attribute
- From: saby
Re: Labels in Virtuoso
- From: trisha.woods
Help! Bus notation on schematics
- From: JC
Re: symbol + schematic pcells
- From: Andrew Beckett
Weird errors, anybody know what sclSetAttribute is/does?
- From: albchen
Re: to run parametric simulation over different corners using analog artist
- From: fogh
Re: Labels in Virtuoso
- From: Tim
Re: debugging Geomstamp errors
- From: Tim
Re: Labels in Virtuoso
- From: S. Badel
Re: calculating a config word during operating point analysis
- From: Svenn Are Bjerkem
how to use awd to view spectre command line simulation results
- From: Allen
Re: how to automatically set a schematic sheet border?
- From: Jos
help for Cadence® Encounter command buildtiminggraph
- From: mediative@xxxxxxxxx
debugging Geomstamp errors
- From: DReynolds
Re: SKILL for DEF importing
- From: trisha.woods
Re: how to automatically set a schematic sheet border?
- From: daytripper
Re: symbol + schematic pcells
- From: Trevor Bowen
Re: Labels in Virtuoso
- From: Bernd Fischer
Re: how to debug geomStamp() errors
- From: Tim
Re: symbol + schematic pcells
- From: fogh
Re: diff between silicon ensemble and soc encounter
- From: fogh
Re: calculating a config word during operating point analysis
- From: fogh
Re: why I can not run assura
- From: Mr. Diva
Re: how to debug geomStamp() errors
- From: Mr. Diva
how to automatically set a schematic sheet border?
- From: Jos
How to Create a dummy two-terminal
- From: tagger
how to debug geomStamp() errors
- From: DReynolds
Re: to run parametric simulation over different corners using analog artist
- From: shanu.sudalai@xxxxxxxxx
symbol + schematic pcells
- From: S. Badel
Re: to run parametric simulation over different corners using analog artist
- From: Svenn Are Bjerkem
Re: to run parametric simulation over different corners using analog artist
- From: shanu.sudalai@xxxxxxxxx
Re: Cadence products installation directory
- From: Andrew Beckett
Re: Does anybody knows how to check phase noise of a divider? Thanks!
- From: Andrew Beckett
why I can not run assura
- From: Yifei Luo
Re: SKILL for DEF importing
- From: rkdocc
Re: how to simulate Vth mismatch in spectre
- From: John O'Donovan
Re: Labels in Virtuoso
- From: trisha.woods
Re: Labels in Virtuoso
- From: Bernd Fischer
Re: Labels in Virtuoso
- From: trisha.woods
Global Find - Concept HDL
- From: G
Re: Labels in Virtuoso
- From: Bernd Fischer
Re: bug in dbCreateLib / ddCreateLib ??
- From: Trevor Bowen
Labels in Virtuoso
- From: trisha.woods
Re: ocnPrint() problem in spectre
- From: vivian
diff between silicon ensemble and soc encounter
- From: eda_cadence
Re: How can I do perematric analysis using spectre command line?
- From: Svenn Are Bjerkem
Re: ocnPrint() problem in spectre
- From: Svenn Are Bjerkem
Re: to run parametric simulation over different corners using analog artist
- From: Svenn Are Bjerkem
how to simulate Vth mismatch in spectre
- From: kalmany
Re: Does anybody use foundry PDK for production chip design?
- From: Trevor Bowen
Re: How can I do perematric analysis using spectre command line?
- From: satya
Re: Fixed: NCSU Extract Problem on Linux
- From: Edward J Kalenda
How can I do perematric analysis using spectre command line?
- From: Allen
SKILL for DEF importing
- From: trisha.woods
Re: bug in dbCreateLib / ddCreateLib ??
- From: Sylvio Triebel
bug in dbCreateLib / ddCreateLib ??
- From: Sylvio Triebel
ocnPrint() problem in spectre
- From: vivian
Re: Does anybody use foundry PDK for production chip design?
- From: Tim
parametric simulation of different CORNERS using analog artist
- From: shanu.sudalai@xxxxxxxxx
to run parametric simulation over different corners using analog artist
- From: shanu.sudalai@xxxxxxxxx
Re: re:schematic not found
- From: Svenn Are Bjerkem
Re: Does anybody use foundry PDK for production chip design?
- From: Bernd Fischer
Fixed: NCSU Extract Problem on Linux
- From: gradjoh
Help: AC Analysis
- From: mxkdirs
AC analysis for a NMOS
- From: mxkdirs
Re: Does anybody use foundry PDK for production chip design?
- From: Edward J Kalenda
Re: How to model a package correctly
- From: Gerry Vandevalk
Does anybody knows how to check phase noise of a divider? Thanks!
- From: wo918
Does anybody use foundry PDK for production chip design?
- From: DReynolds
Re: calculating input impedance
- From: Allen
calculating input impedance
- From: jbxvt
re:schematic not found
- From: arsenal
Re: How to make the output of spectre as text format in a file
- From: Andrew Beckett
Re: simulation problem
- From: Andrew Beckett
Re: schematic not found
- From: Andrew Beckett
PSS simulation - nodal impedance simulation
- From: Yanyu
Re: How to make the output of spectre as text format in a file
- From: Roger Light
Re: how to adjust parameters of low hierarchy
- From: Bernd Fischer
re:how to adjust parameters of low hierarchy
- From: bowling
re:how to adjust parameters of low hierarchy
- From: bowling
Re: why my shcematic look yellow?
- From: Svenn Are Bjerkem
Re: re:schematic not found
- From: Svenn Are Bjerkem
Re: How to make the output of spectre as text format in a file
- From: Svenn Are Bjerkem
Re: why my shcematic look yellow?
- From: okguy
why my shcematic look yellow?
- From: arsenal
re:schematic not found
- From: arsenal
Re: Why won't schPlot() work here?
- From: leddedup
Re: How to make the output of spectre as text format in a file
- From: vivian
Re: How to make the output of spectre as text format in a file
- From: vivian
How to make the output of spectre as text format in a file
- From: vivian
Re: simulation problem
- From: Bernd Fischer
simulation problem
- From: daniel
Re: how to adjust parameters of low hierarchy
- From: Svenn Are Bjerkem
Re: Inactive recompile menu item in file manager
- From: Svenn Are Bjerkem
Re: how to adjust parameters of low hierarchy
- From: Bernd Fischer
Re: Inactive recompile menu item in file manager
- From: Bernd Fischer
Re: Why won't schPlot() work here?
- From: Sam
how to adjust parameters of low hierarchy
- From: bowling
Inactive recompile menu item in file manager
- From: Svenn Are Bjerkem
7WL problem
- From: oceandai
How to model a package correctly
- From: oceandai
About corner simulation
- From: Dmitriy Shurin
Re: Why won't schPlot() work here?
- From: leddedup
calculating a config word during operating point analysis
- From: Svenn Are Bjerkem
Re: Why won't schPlot() work here?
- From: PM
Re: XL update source
- From: Tim
Re: layoutXL vs. mosaics
- From: Tim
Re: spectre netlist visualization
- From: Andrew Beckett
Re: SKILL - Net cross-probing in Virtuoso Layout Editor
- From: Gerry Vandevalk
Re: SKILL - Net cross-probing in Virtuoso Layout Editor
- From: Gerry Vandevalk
Re: Why won't schPlot() work here?
- From: leddedup
Re: spectre netlist visualization
- From: Bernd Fischer
spectre netlist visualization
- From: Thomas Popp
Re: layoutXL vs. mosaics
- From: Jean-Marc Bourguet
Re: Why won't schPlot() work here?
- From: PM
Re: substrate noise
- From: Kp
Re: Assura LVS problem
- From: neo
Why won't schPlot() work here?
- From: leddedup
re:how can i do fft in analog artist?
- From: arsenal
Re: SKILL From the command line in Linux
- From: Bernd Fischer
Re: SKILL From the command line in Linux
- From: stefano zanella
SKILL From the command line in Linux
- From: leddedup
Re: layoutXL vs. mosaics
- From: Andrew Beckett
Re: schematic not found
- From: Andrew Beckett
Re: Differential mixer simulation problems with 4.4.6
- From: Andrew Beckett
Re: Saving results of Monte Carlo simulation in OCEAN
- From: Andrew Beckett
Re: SKILL - Net cross-probing in Virtuoso Layout Editor
- From: Andrew Beckett
Re: Is the spectreVerilog simulator much faster with IC/5.1.41_usr2 than with IC/5.0.33 ?
- From: Andrew Beckett
Re: XL update source
- From: Andrew Beckett
Re: Assura LVS problem
- From: Bernd Fischer
Re: how can i do fft in analog artist?
- From: Gerry Vandevalk
Re: Importing DEF file in Cadence DFII
- From: Gerry Vandevalk
Cadence products installation directory
- From: okguy
Re: how can i do fft in analog artist?
- From: sheldonbrand
Re: Assura LVS problem
- From: neo
Noise models in BSIM3 and BSIM4
- From: mayank
schematic not found
- From: arsenal
Re: HSpice and Spectre Model differences
- From: fogh
Re: Importing DEF file in Cadence DFII
- From: fogh
re:SKILL - Net cross-probing in Virtuoso Layout Editor
- From: DReynolds
Re: inserting label in encounter
- From: Kp
Re: Assura LVS problem
- From: Bernd Fischer
Re: Assura LVS problem
- From: neo
Re: Assura LVS problem
- From: Bernd Fischer
Assura LVS problem
- From: neo
PSS plot form bug?
- From: bsimtim
Re: Importing DEF file in Cadence DFII
- From: trisha.woods
Cannot create Abstracts
- From: Guenther Sohler
Re: substrate noise
- From: okguy
Re: SKILL - Net cross-probing in Virtuoso Layout Editor
- From: Katie
Re: SKILL - Net cross-probing in Virtuoso Layout Editor
- From: Katie
layoutXL vs. mosaics
- From: danmc
Re: Importing DEF file in Cadence DFII
- From: Gerry Vandevalk
Re: Importing DEF file in Cadence DFII
- From: jayl-news
Re: substrate noise
- From: Gerry Vandevalk
Importing DEF file in Cadence DFII
- From: trisha.woods
Re: inserting label in encounter
- From: saby
Re: XL update source
- From: Tim
Re: XL update source
- From: Bernd Fischer
XL update source
- From: Tim
Capture CIS and PSpice simulation problem (SPD)
- From: Talez
Re: Is the spectreVerilog simulator much faster with IC/5.1.41_usr2 than with IC/5.0.33 ?
- From: Frank Buergel
substrate noise
- From: Kp
Re: inserting label in encounter
- From: Kp
Re: SKILL - Net cross-probing in Virtuoso Layout Editor
- From: Fergus_S
Drive Resistance in Ceff Calc
- From: Sampath Dechu
Re: SKILL - Net cross-probing in Virtuoso Layout Editor
- From: tattvamasi@xxxxxxxxx
Re: how can i do fft in analog artist?
- From: Gerry Vandevalk
Re: SKILL - Net cross-probing in Virtuoso Layout Editor
- From: Gerry Vandevalk
how can i do fft in analog artist?
- From: arsenal
Re: SKILL - Net cross-probing in Virtuoso Layout Editor
- From: Edward J Kalenda
SKILL - Net cross-probing in Virtuoso Layout Editor
- From: Katie
Re: Layout dynamic highlighting lpp?
- From: Gerry Vandevalk
Re: cellview selection in CDF
- From: Andrew Beckett
Re: cellview selection in CDF
- From: Gerd
Re: Layout dynamic highlighting lpp?
- From: okguy
Saving results of Monte Carlo simulation in OCEAN
- From: guan1121
inserting label in encounter
- From: saby
Re: cellview selection in CDF
- From: Andrew Beckett
Re: Is the spectreVerilog simulator much faster with IC/5.1.41_usr2 than with IC/5.0.33 ?
- From: Andrew Beckett
Re: Layout dynamic highlighting lpp?
- From: Kholdoun TORKI
Re: Layout dynamic highlighting lpp?
- From: Kholdoun TORKI
cellview selection in CDF
- From: Gerd
About load-pull simulation
- From: Yanyu
Re: Layout dynamic highlighting lpp?
- From: Bernd Fischer
Re: process independent netlisting from ADE
- From: fogh
Re: Layout dynamic highlighting lpp?
- From: jorobins
Re: Documentation for the program psf
- From: Andrew Beckett
Re: Schematic pin to pin tracer
- From: Assura User
Re: Layout dynamic highlighting lpp?
- From: okguy
Re: Layout dynamic highlighting lpp?
- From: jorobins
Re: HSpice and Spectre Model differences
- From: mayank
Re: Layout dynamic highlighting lpp?
- From: Bernd Fischer
Re: HSpice and Spectre Model differences
- From: Bernd Fischer
Documentation for the program psf
- From: Svenn Are Bjerkem
Documentation for the program psf
- From: Svenn Are Bjerkem
Is the spectreVerilog simulator much faster with IC/5.1.41_usr2 than with IC/5.0.33 ?
- From: Frank Buergel
Re: HSpice and Spectre Model differences
- From: mayank
Layout dynamic highlighting lpp?
- From: jorobins
Free netlist ECO tool
- From: Heidi
Free netlist ECO tool
- From: Heidi
Re: Schematic pin to pin tracer
- From: Heidi
Re: callback functions
- From: Edward J Kalenda
callback functions
- From: JD
Differential mixer simulation problems with 4.4.6
- From: Jack Luminous
Re: gpdk
- From: J. J. G.
Re: gpdk
- From: J. J. G.
Re: SRR available yet?
- From: Andrew Beckett
HSpice and Spectre Model differences
- From: mayank
Re: SRR available yet?
- From: Svenn Are Bjerkem
Re: Customizing Library Manager
- From: Andrew Beckett
Re: Library Manager - new Library
- From: Bernd Fischer
auCdl netlisting with '_ansCdlCompParamPrim'
- From: Gerd
Re: process independent netlisting from ADE
- From: stroller
Re: Schematic pin to pin tracer
- From: J. J. G.
Re: process independent netlisting from ADE
- From: tattvamasi@xxxxxxxxx
Re: process independent netlisting from ADE
- From: stroller
Re: process independent netlisting from ADE
- From: stroller
Re: design design package tutorials
- From: Assura User
Re: hiGetTextFieldFit()
- From: Pete nospam Zakel
Re: process independent netlisting from ADE
- From: tattvamasi@xxxxxxxxx
Re: Schematic pin to pin tracer
- From: tattvamasi@xxxxxxxxx
Re: Schematic pin to pin tracer
- From: tattvamasi@xxxxxxxxx
Re: Schematic pin to pin tracer
- From: J. J. G.
Re: process independent netlisting from ADE
- From: stroller
Re: Library Manager - new Library
- From: Guenther Sohler
Re: Library Manager - new Library
- From: Roger Light
Library Manager - new Library
- From: Guenther Sohler
Re: hiGetTextFieldFit()
- From: redhavoc
Re: SKILL Qn: How to get the user select only a particular obj type
- From: Suresh Jeevanandam
design design package tutorials
- From: aravindhere
Re: process independent netlisting from ADE
- From: Andrew Beckett
Re: Seeing noise anlaysis in spectre
- From: Dmitriy Shurin
Re: hiGetTextFieldFit()
- From: Pete nospam Zakel
process independent netlisting from ADE
- From: stroller
Schematic pin to pin tracer
- From: tattvamasi@xxxxxxxxx