Re: More blather about atom

Hello all,

"Quadibloc" <jsavard@xxxxxxxxx> wrote in message
On Apr 9, 6:01 pm, "Andy \"Krazy\" Glew" <a...@xxxxxxxxxxxxxxxxxx>

That's the basic approach I espouse - convert Itanium to uops, and
execute on whatever OOO core keeps your x86 workload happy. Except that
Itanium is so big and complicated, and has so many registers, that it
necessarily demands a more complicated OOO core than is necessary for
x86 or RISC alone.

Ah. Except for having more registers, and the ability to switch to big-
endian mode, I thought that the Itanium couldn't really do anything an
x86 couldn't do. In fact, it can do even _less_ than the x86, being
missing a divide instruction.

Otherwise, their instruction sets appeared virtually identical,
leading me to wonder why they waste so much effort designing the
Itanium chips independently of the x86 chips. Apparently I haven't
read the Itanium documentation carefully enough when I came to that
conclusion. Or it could be that the number of registers critically
affects how OOO logic works.

"Terje Mathisen" <"terje.mathisen at"> wrote in message
A _far_ more complicated core:

You pretty much have to have support for predicated everything, for the
SW alias detection and the rotating register sets.

Right, predication is just the beginning. You have:
1) NAT bits (all registers are 65 bits, pushes and pops accumulate extra
bits into separate registers (one for user pushes, one for RSE)
2) The RSE. The logic for this broke several interns.
4) Predicate registers (can write two distint regs "p2,p36 = cmp r1, r2").
Also, you can write all the rotate controls (p48..63?). And all at once.

That's just off the top of my head. There is probably more :)

Best to think of Itanium as an OOO personality trapped in an in-order body.
The ISA attempts to enable OOO... (but in a twisted and evil way, like
people who hate OOO think about OOO).