Re: Question on Lynnfield chip layout


"Terje Mathisen" <Terje.Mathisen@xxxxxxx> wrote in message
news:qcSdnejIo-XvGGjXnZ2dnUVZ8uOdnZ2d@xxxxxxxxxxx
Stephen Fuld wrote:
Brett Davis wrote:
Actually I spoke too quick, I believe that generally the L3 only
holds
data that is committed to RAM. So a dirty L2 cache line that gets
evicted to L3 would also be written to RAM. Makes the L3 simpler
to
implement, fewer tag bits and checks, easier to replace lines,
just
overwrite.

Really??? Then the L3 is basically a giant store queue. It doesn't
hold
clean data that has been evicted from the L2 due to the L2's
limited
capacity. That sure seems odd.

I agree.

Particularly since the L3 is shared, it seems a given that it can be
the source of a cached load for any of the cores on the chip.

Terje
--
- <Terje.Mathisen at tmsw.no>
"almost all programming can be viewed as an exercise in caching"

Perhaps he meant to say the L3 is "store through" rather than the L2
"store in" which does mean there is never dirty data in cache. When
clean data is evicted from L2 isn't it just written over? So whether
there is a copy in L3 depends on the L3 traffic and replacement
algorithm, doesn't it?

del


.

Quantcast