Re: The coming death of all RISC chips.

Its hard work getting to be a architect.

BTW: IMO, the job of a computer architect is NOT to come up with
brilliant micro-architecural features; its to balance the competing
requirements. If its done correctly, you get an elegant design,
where
everything fits together just right, and if any part were changed,
things would fall apart.

No, it just takes doing your homework, just look at PowerPC, the
only
CPU where the instruction set designers actually did do their
homework.

Brett

If you believe that full custom layout can just be handed to the
servers to do, why should I believe anything else you say? You make
many assertions about things and people. Why should we take any of
them seriously?

Did you work for any of IBM, AMD, Apple, Intel, HP? Or is this all
hearsay?

del

I have pointed out that I am a software engineer, not hardware, and I do
not work with hardware designers, much less CPU designers. It is a given
that as a result I am going to say something incredibly stupid from a
hardware guys point of view now and again. Feel free to call me on it,
both I and lots of other readers will learn something from the exchange,
which is the reason most of us are here.

It was probably my previous post which set you off, yes in software I am
pretty close to all knowing, and like most bright people I occasionally
come up with good ideas in other fields, like CLIW.

If I switched to hardware design I would be the student for the next two
years, not the master, after which I would impress the boss with an
occasional unexpected innovation. Add another half decade before I think
I have attained a similar level of skill in hardware that I do with
software, and another half decade on top of that before I actually do. ;)

Even for someone as supremely confidant as I, it would take a decade to
get into your league, assuming I am successful, which is not a given as
phrased above.

As a bright software guy in the peanut gallery I am reasonably happy
with the one off answers I gave to the one off questions. In particular
the phrase "full custom layout" without qualifiers means different
things to different people, and is actually a grab bag full of dozens of
tasks. Being the last bullet point, my assumption is that he was in
general referring to the final task where the chip layout is optimized
for size. A server farm does this, being careful not violate line
lengths which would break the logic, or cause critical speed path
issues, etc. This is a complicated task that requires a team of hardware
engineers (and a few software engineers) to nurse maid to conclusion,
which sometimes takes months.

I could given that much longer answer to all the questions, but it would
not have aided the conversation, more likely bored some readers to tears.

And yes a lot of my general knowledge is hearsay, here are some hearsay
links on the Itanic development from a hardware engineer on the inside:

A quick insider's history of Itanium I:
http://hardware.slashdot.org/comments.pl?sid=1129041&cid=26870323

A quick insider's history of Itanium II:
http://hardware.slashdot.org/comments.pl?sid=1129041&cid=26872629

It looks like from the Top Intel Executives point of view Itanic was
just a scam to kill off RISC chip competition. I bet they knew the
design was flawed and unlikely to do any better than a RISC chip, but if
Itanic succeeded so much the better. Its a Win Win regardless, no down
side to a monopoly that can squander billions designing Itanic and not
care about the cost. The marginal profits gained from killing the RISC
chips probably roughly equalled the cost spent.

For Intel Itanic was not a mistake, it was a marketing master stroke
that increased Intels profit AND monopoly safety (reduced competition)
regardless of the outcome.

Brett
.

Relevant Pages

  • Re: Security and EOL issues
    ... OS software resources are designed that reserved ram and disk space among other resources, to reflect what current hardware size is available. ... (There was a security patch a few years ago that could not be applied to NT4 as it required more resources then NT4 could provide. ... Installing air bags requires that the automobile manufacturer design, test, ... Computer Emergency Response Teams, and Digital Investigations. ...
    (Security-Basics)
  • Re: Now THIS is Meshuga - Do NOT bring your IPad to Israel
    ... can't write applications for the iPad without having one. ... When you write a novel, you would prepare and outline, design how ... wrote the specs for the next product while the developers where still ... So as I said before, you don't need the hardware to write code, you ...
    (soc.culture.jewish.moderated)
  • Staff HW Engineer ~ Lead Us to ATCA & Beyond in Your End-to-End Board-Level HW Desig
    ... The senior level hardware engineer looking for the product realization ... and true ownership that comes with full end-to-end board-level hardware ... help us retain dominance in the design of high performance switching ...
    (comp.arch.embedded)
  • Re: 10khz DBSK decoder
    ... In an AVR, you may want to come closer to the 'hardwareish' thing: run the whole thing as a Costas loop or as a signal-square-and-PLL, and do integrate-and-dump. ... In retrospect, the ISR should have just taken ADC samples and shoved them into a queue, then set a flag. ... But I had never seen that design pattern, so it just ran with that big bloated ISR... ... You'll get more consistent timing if you can trigger your ADC from hardware and interrupt on the end of conversion pulse. ...
    (comp.dsp)
  • Re: For loop synthesis and repeated structures, any examples?
    ... I meant that the for loop IS an innefficient constuct ... in the sense that it would paralellise the hardware... ... has almost nothing to do with that design compromise. ... the multiplier, and capturing its output into the right ...
    (comp.lang.verilog)