Re: The coming death of all RISC chips.

On Apr 17, 1:13 am, Jacko <jackokr...@xxxxxxxxx> wrote:
On 17 Apr, 05:33, Robert Myers <rbmyers...@xxxxxxxxx> wrote:

On Apr 16, 10:37 pm, Jacko <jackokr...@xxxxxxxxx> wrote:

By the way, not having conditional branching solves some pipeline
stalls, but conditional assignment does not solve data dependancy
sufficiently to extract efficient performance from speculative
execution and ILP.

That's a pretty strong statement.  I'd be interested to know if you
considered that to be true even leaving power constraints aside.

Robert.

if efficiency is not defined in terms of power, what alternate word
would you suggest so that I may consider the truth of the inefficient
system suggested?

I looked back over your posts to see where you had made the efficiency
proviso and couldn't find it.

Most strategies to make things happen faster have negative
consequences for power consumption.

If power were not a consideration, there are all kinds of wild run-
time strategies like speculative execution (for which the schemes can
be very elaborate) that would, at least in theory, get arbitrarily
close to optimal execution.

It's only when you have to decide which things are worth the extra
transistors and the extra watts that the problem starts to look truly
intractable and not merely complicated: to decide whether speculation
is worth it, you need to know more about the future than you generally
do know.

I agree with you that ILP is complicated. The sweeping conclusions
that are so common on this subject, though, aren't helpful. With a
real marketplace, real transistors, real software, and real compilers,
one incredibly ambitious effort was a huge disappointment, and that's
about all you can say, grandiose claims to the contrary
notwithstanding.

The importance of power consumption makes it seem unlikely that
anything other than compiler and software research will be attempted
in the foreseeable future.

You know my view, very simple cores, even to the extent of 1
instruction per 2 or 3 cycles, and a simple instruction at that.

Speculative execution is a waste of a threading execution potential.
Instruction level parallelism happens to some extent on a sub
instruction (e.g. pre post inc/dec) basis. Whether it it better to
split complex instructions into VLIW and end up clogging the register
file ports with strange multiplex strategies is debatable.

Consider this ... If the utilization of an extra functional unit is
limited by extractable ILP limits, then surly having the unit use
specialist registers whose contents are filled and emptied que fashion
into and out of the main nregister file (lower mux overhead) then the
opcode for this functional unit can be smaller, and possibly just 1
bit.

Maybe from an architect's POV, the problem is what to do with extra
available transistors. From a certain kind of users' POV, the
question is how to get results to arrive sooner. If you *really* need
the extra performance that exotic execution schemes would buy you and
you *really* don't care about power consumption, maybe heroic cooling
and materials research are better avenues to explore.

Robert.
.

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