Re: The coming death of all RISC chips.

Jacko <jackokring@xxxxxxxxx> wrote:
No need to build a big statue, just a 1cm high one welded onto the
sholder of faraday down the embankment.

http://nibz.googlecode.com

You are obviously feeling left out, I did look at your NIBZ design.
NIBZ is an angle on the MISC (Minimum Instruction Set Computer) with
some newer hardware angles thrown at it to make the design even smaller.
(Sharing parts between pairs of CPUs, etc.)

The basic problem is that todays level of integration has made all MISC
designs obsolete. You can buy a ATI chip with 800 vector processors with
128 vector registers each. You could easily fit a dozen of your NIBZ
processors in the space of one of those vector processors. But how in
the hell are you going to wire up those 10,000 NIBZ cores and succeed in
getting any useful work out of them. The interconnect design is
impossible, and the software design for the networking is worse.

When it comes to getting work done 800 gas guzzling SUVs will beat the
crap out of 10,000 unicycles every time.

The problem today is an embarrassment of riches, which tends to embolden
bloat, and then the bloat slows you down and costs you cycles, and heat,
and clock, and die area, etc.

You also have obsolete ideas like RISC which are slow to die, once upon
a time ago RISC made excellent sense for hardware AND software, but time
has moved on.

We have three levels of cache today on a modern CPU, because the first
two cannot be made any bigger without making them slower. Huge bloated
32 bit VLIW instructions that spill out to L2 and L3 are just a bad idea
today.

Today you want to compress your instructions down, fitting almost twice
as many in that limited L1 and L2, giving you a big boost in performance
for almost free. Also with variable width instructions this enables you
to come up with those long instructions that will give you a performance
advantage where you need it.

Anyone that has worked with SSE2 or Altivec knows that CPU design is
trying to advance, but we are being held back by what we can put into
the limitations of 32 bit VLIW instructions.

We have a new design, we just need an acronym to rule them all. ;)

Brett

VWI - Variable Width Instructions. To literal, wont sell.
AIEX - Advanced Instruction EXtensions. Much better, but not quite.
AISE - Advanced Instruction Set Extensions. Sound not right.
MISE - Modern Instruction Set Extensions. I kinda like this one. ;)
AWE - Advanced Wide Extensions. NICE.
MAWE - Minimal And Wide Extensions. GOOD.
WASI - Wide And Small Instructions.

New acronyms welcome. ;)
.

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