Re: The coming death of all RISC chips.

On 4 Apr, 01:47, Mayan Moudgill <ma...@xxxxxxxxxxx> wrote:
Jacko wrote:
RISC is essential to reduce core area. This is important for
interleaving core gates into the memory array.

cheers jacko

Area-wise, its not clear that RISC is the way to go. The decoder on a
chip is generally a small fraction of the total area. A simplistic
argument is: RISC require smaller decoder. However, the instructions are
bigger. So, the instruct-cache has to be larger. The increased area of
the instruction-cache is much larger than the saving due to the decoder.

Of course, its not that straight-forward. But the trade-offs are too
complex for anyone who makes a statement like "RISC is essential to
reduce core-area" to comprehend.

Who says the instruction area is more complicated?

Reduced Instruction Complexity Computer.
===============================
All instructions are removed and logic area simplified till the
instruction stream fits in a nibble or less per instruction.

Implications:
1. The instruction width is small.
2. The CPU area is low
3. Any instruction cache is layered into an instruction stream and a
subroutine address and literal cache
4. High code density is achived by a compact subroutine calling
instruction cache. The effective area of this cache may be reduced by
noting that only certain values of subroutine entry point and literal
values are ever used. So a cache of used addresses and literals, is
complimented by an execution order index into the subroutine and
literal value cache.
5. The instruction cache may be bigger using the above method when
large number of cores all have small instruction caches.
6. The cache values are moved with the register set toward the memory
on which execution next depends.
7. The memory is placed on the chip as the L2 cache, and the small
DRAM L3 memory segment
8. Multiplex decode logic of the memory is reduced due to segmentation
of memory any core will access.
9. Each core executes and latches into the next core's register and
L0,L1 static latches. In this way execution will eventually reach the
require core linked to the required memory. There may be cross
coupling between L2 caches by exchange too. Occasional optional on
address in register loopbacks of state may improve seek performance of
this solid state DPU (Distributed Processing Unit).

If you can make a CISC with less gates and registers please do tell.

cheers jacko
.

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