Re: Intel publishes Larrabee paper

Terje Mathisen <"terje.mathisen at tmsw.no"> writes:
Glen Herrmannsfeldt wrote:
Terje Mathisen wrote:
(snip)

The original 064 chip only supported 32 and 64-bit load/store
operations

But Alpha still was byte-addressed.

probably because the architecture team thought they would
be able to fake the needed byte and half-word operations, a decision
they had to reverse at a later date.

Stories that I heard was that it was needed such that MS
would port NT to Alpha. The other OS could live without it.

Not needed for NT, but lots of third-party drivers would access
memory-mapped devices which had 8 or 16-bit ports packed together.

Doing a 64 or 32-bit read/modify/write cycle to store a single byte
would have very "interesting" results.

I believe they had to use a hw hack where two extra addressing ranges
were setup, where load/store would work in 8 or 16-bit chunks.

Yes.

Besides all this, I still remember reading the original architecture
manual and posting here at the time, about how you needed an
11-instruction sequence to write an arbitrarily aligned subword.

Yes. However, that sequence was apparently extremely rarely used.
Gas had a bug where it generated the wrong sequence for the ustq,
ustl, and ustw, and apparently nobody noticed that for many years:

http://sourceware.org/bugzilla/show_bug.cgi?id=4124

- anton
--
M. Anton Ertl Some things have to be seen to be believed
anton@xxxxxxxxxxxxxxxxxxxxxxxxxx Most things have to be believed to be seen
http://www.complang.tuwien.ac.at/anton/home.html
.

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