Re: after SIMD implementation, is it still a RISC?

Terje Mathisen <terje.mathisen@xxxxxxxxxxxxx> writes:
Even with my possibly (probably?) biased x86 background, I really don't
think having Load-Op should disqualify an architecture from being "RISC":

No RISC architecture has it, and "load/store-architecture" is deemed
as one of the defining properties of RISC, so I think the jury has
decided on that. The reasons are probably:

* Separating the load from the operation allows the compiler to
schedule the load earlier and schedule something else in the load
delay slot.

* RISCs have more registers, so they can keep more variables in
registers, avoiding the need to access them in memory, so load-operate
instructions would see less usage.

* Typical RISC instruction formats have only one register left in a
memory-format instruction; that register would have to serve as both
source and destination of the operation, making register allocation in
the compiler more complicated. Alternatively, one would have to
shorten the offset in the memory-format instructions to make room for
an additional register.

This is a sufficiently common pattern that it is worthwhile to allow
this instruction type simply to save code bandwidth.

AFAIK even Thumb does not have load-operate instructions, so they did
not think it worthwhile.

IMHO RISC should be about making cpus simple enough that you can say
they "obviously have no bugs", rather than "no obvious bugs", but
history has shown that they are all definitely in the second category
anyway. :-(

RISC was about speed, not (particularly) correctness.

- anton
--
M. Anton Ertl Some things have to be seen to be believed
anton@xxxxxxxxxxxxxxxxxxxxxxxxxx Most things have to be believed to be seen
http://www.complang.tuwien.ac.at/anton/home.html
.

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