Re: after SIMD implementation, is it still a RISC?
- From: Quadibloc <jsavard@xxxxxxxxx>
- Date: Tue, 2 Sep 2008 08:42:02 -0700 (PDT)
On Aug 30, 2:46 pm, an...@xxxxxxxxxxxxxxxxxxxxxxxxxx (Anton Ertl)
wrote:
MitchAlsup <MitchAl...@xxxxxxx> writes:
There are those who will take the position that RISC has to be exposed
in the instruction set {SPARC, MIPS, Alpha,...}. The applicable
characteristics are: a) Load/Store, 2 Operand 1 Result instructions,
with the capability of only a single exception/instruction.
Everyone I respect takes this position, so I am surprised to read this:
I, for one, would classify Athlon and Opteron as RISC.
If AMD64 is RISC, then RISC is meaningless.
This is true. The K5 and K6 were described in the media as converting
x86 instructions to RISC, but in fact this was a garbled explanation
of what they really were; machines with a decoupled microarchitecture.
This decoupling does involve separating out the memory fetch and
operate parts of a typical CISC memory-reference instruction, so an
aspect of the RISC philosophy has had an influence on the
implementation, but the ISA is still CISC.
Of course, in the very early days of RISC, it was said that to be RISC
one had to have every instruction execute in a single cycle. So you
could not have floating-point and RISC. The definition has changed.
To answer the OP's question, then, MMX-type instructions do not stop a
processor from being RISC, since the PowerPC, a RISC architecture, has
AltiVec. Not as RISC is currently understood.
John Savard
.
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