Re: Larrabee details: Yes, it is based on the Pentium. :-)


"ChrisQ" <blackhole@xxxxxxxxxxx> wrote in message news:g6coqj$44s$1@xxxxxxxxxxx
Bengt Larsson wrote:


I also seem to remember that ARM is hard to scale up in performance, if you want to do that. Although I admittedly
don't remember what feature it was that made it so.

ARM has no feature that makes it hard to improve performance.
There are now various 2-way superscalar ARMs running at 1+GHz.

I don't have enough background either, but have just started looking at
arm for higher end embedded work and although various vendors have
glued on a vectored interrupt block, the core still appears to have a
6502 style interrupt structure (NMI/IRQ etc. Looks like it needs quite a bit
of support from software. A great disappointment after years of 68k etc
work, where the fully vectored interrupts are completely transparent at
software level. Even the Renesas 16 bitters have a traditional vector
table approach, while the arm organisation just looks like hard work and
is overcomplex.

Vectored interrupt controllers are used in most ARMs, so there isn't any
extra software complexity. Many compilers allow you to write interrupt
routines in C. The Cortex-M3 has an architecturally defined interrupt
mechanism with priorities, preemption and tailmerging of interrupts.

Wilco


.

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