Re: www.sicortex.com

On Apr 10, 7:13 pm, matt.rei...@xxxxxxxxxxxx wrote:
On Apr 9, 12:51 pm, already5cho...@xxxxxxxxx wrote:



Thanks for information, Matt.
I vaguely remember from the Byte articles from the mid 90s that 5Kf
FPU was optimized toward single-precision performance. Did you change
this part of the core?

We did goose the FP unit a bit. We rebuilt the FP pipeline to support
double precision at 2FLOPs per cycle (MADD.D a double precision
mull-add), so the double precision FP rate is the same as the single
precision FP rate.


Very well


Other than that, we added cache coherence to the L1, and full
single bit correction/double bit detect to the L1 Dcache. (The I
cache is parity protected.)


For massively-parallel scientific workloads ECC (if it is actually
ECC) on L1D cache sounds to me like over-engineering. But what I know?

There were Byte articles in the mid 90's on the 5Kf? Who knew?

Power of Internet: http://futuretech.blinkenlights.nl/byte.html
.

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