Re: An efficient marriage between memory and chips...

On Feb 25, 5:26 pm, "Chris Thomasson" <cris...@xxxxxxxxxxx> wrote:
"John Dallman" <j...@xxxxxxxxx> wrote in message

news:memo.20080225215031.1804I@xxxxxxxxxxxxxxxxxxxxxx

In article <iv2dnckE5rGjYlzanZ2dnUVZ_sedn...@xxxxxxxxxxx>,
cris...@xxxxxxxxxxx (Chris Thomasson) wrote:

I think that this would require the chip vendor to create specialized
memory for their processors. I was thinking that memory bank could
hold 4 physical chips. Each chip would have direct access to
multiple-MB (2 or 4 MB) of "local" storage.

Much bigger than that, one hopes: that's a decent-sized cache these
days, not main memory.

Right... I was not really trying to directly connect the chips to the
main-memory, I just wanted there to be a fairly large amount of local
memory. I think it would be nice for a processor to have several MB's of its
own dedicated memory. IMHO, its a worthwhile effort to decrease the distance
between the chip's and memory.

It is of you're a computer programmer, but not if you're an
engineer.
Which is really where the success of fiber optics, laser disks,
optical computers, and robots fit into the computer arch scheme.




I am not a hardware guy in any sense of the
term. The post from Mitch Alsup tells me that it would a fairly tedious task
to integrate with enough memory to run an operation system which needs a lot
of resources.

In other words, per-chip memory is converted into per-core memory.
This thing would have a distributed multi-threaded programming model.
Do you think such a beast could possibly work? Or is it even feasible?

You need to read up on NUMA systems in general, several kinds thereof.
Look at the big Suns, the big SGIs and Crays. Currently, you're missing
some basic concepts.

I was just thinking in very basic terms of local-memory access = fast,
remote-memory access = slow. IMHO, that scheme fits in well with basic NUMA
programming techniques.

.

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