Re: Fantasy-Land Hierarchal NUMA Memory-Model on Vertical Multi-Core/Memory Cube-Processing Unit.

"MitchAlsup" <MitchAlsup@xxxxxxx> wrote in message news:ce6f2f29-b878-42e7-948d-a73a45f065c3@xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
On Feb 14, 4:16 am, "Chris Thomasson" <cris...@xxxxxxxxxxx> wrote:
The physical size of a single liquid-cooled processing-unit would be
4"x4"x4" in the form of pluggable processing entities, that connect directly
into the motherboard of a super-computer which can indeed fit "comfortably"
under a given company's "average" desk size per-office.

Lets say, for example, that we make this monster from 12mm*12mm*1mm
processor chips with all the usual stuff on die (CPU, cahces,
crossbars, controllers) and a 3D interconnect scheme. Thus, this 4*4*4
cube would house some 8*8*100 of these dies all packed together
nicely. Thus, we now have an energy density (at 100W/die) of 64KW in a
cube the size of a light bulb. But let us ignore that minor heat flow
problem for now.

Let us assume you intend to mount this chip via a socket on the
motherboard. So, we now have 640,000 processors (single CPU/die)
consuming memory bandwidth through 9000-20,000 pins. As they say in
the hills: "Ain't gonna verk". You are off by a factor of 100 in the
vpin interconnect (minimum); even if the pins are all wiggling at
3+GHz. But lets ignore this (again) for now.

The motherboard will have to support some 640,000 DRAM DIMMs (for
adequate memory footprint and adequate BW) and have these all within
about 10" of the cup cube (acceptable latency). I think there is a
fundamental limit to supercomputing that will stymie this effort far
before we get to the 4*4*4 cube. And this limit is the number of pins
(or amount of information) that can pass through the surface area of
that cube (per unit time).

[...]

Points well taken. Okay... Well, I guess I could reduce the idea down to an integration of a fairly large amount of memory directly into the cores of a single processing-cube. Something like 8 Cores with hundreds of kilobytes (6-7 hundred) of per-core memory, perhaps even a 1MB per-core... This would be NUMA setup, with DMA channel interface for inter-core communication. Like the Cell processor. The memory connects can site directly below and on top of the "cpu-layer". Like a sandwich with memory layers for bread, and cpu layer for meat. Is that feasible?

.

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