Re: Does RISC still offer a significant numbercrunching advantage?

On Dec 3, 4:19 am, Andrew Reilly <andrew-newsp...@xxxxxxxxxxxx
users.org> wrote:
On Sat, 01 Dec 2007 11:05:11 +0100, Terje Mathisen wrote:
I believe IBM Power and possibly Itanium have the highest absolute
SPECFP scpres,

Is there a concise analysis of what the specific advantages are, here?
In the past, it seemed to be mostly because both Power and Itanium (and
Alpha, in its day) had two full sets of FP multipliers and adders, where
the x86 and amd64 processors only had half, or one (albeit with SIMD of
some sort).

Nitpick - Alpha never had two full sets of FP multipliers and adders.
May be, it was planned for EV8, I don't know, but shipping Alpha
products had one FP multiplier and one adder.

However the Core2-series seems to have the same two sets of
FPUs, so that should now be a wash, right? What else is different?
Cache size seems likely, but is there still a register set size effect?
Something to do with memory system performance? Some measurable net
detriment due to longer pipelines doing instruction decode?

Cheers,

Andrew

As Terje already pointed out, the absence of non-destructive
operations is the biggest drawback of IA-32/AMD64 instructions set for
number crunching applications.
The shortage of architected register is secondary to that esp. for
AMD64 that have 16 SSE registers.
An absence of FP_MAC is not a big drawback in my opinion and may be
even advantage (helps to keep max. power consumption under control).
However I am biased in that regard. I just don't like FP_MAC.

.

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