Re: mainframe performance, was Is a RISC chip more expensive?

Stephen Fuld <S.Fuld@xxxxxxxxxxxxxxxxxxxx> writes:
The general consensus that led to RISC systems was that a sequence of
RISC instructions was at least as fast, and usually faster than a
heavily microcoded instruction for accomplishing complex tasks. So
what is it about the microcode assists that changes this consensus?

other post in this thread
http://www.garlic.com/~lynn/2007o.html#35 Is a RISC chip more expensive?

fort knox and related activities ... replacing large variety of
different microprocessors with 801 "iliad" processors was more
about eliminated huge amount of hardware and software investment
in constantly developing and supporting different processors.
misc. past posts mentioning romp, rios, 801, iliad, fort knox,
etc
http://www.garlic.com/~lynn/subtopic.html#801

the big thing in microcode assists was that typical 370 mainframe
implementation for the low-end and mid-range machines involved
microprocessors with an avg. of ten microprocessor instructions executed
for every 370 instruction emulated. something similar is currently
observed in the 370 emulators implemented on i86 platforms.

the 138/148 ecps microcode assist identified high-use kernel
code paths and architectected mechanism that took critical
(370 mainframe) code sequences and moved them into native
processor engine ... for a 10:1 performance improvement. This
issue is orthogonal to whether the native engine was cisc
or a 801 iliad processor. for other drift ... old email
mentioning 801
http://www.garlic.com/~lynn/lhwemail.html#801

there was another class of virtual machine microcode assists that gained
performance by avoiding context switch. a "privilege" instruction
involved interrupt into hypervisor kernel, context change and state
save, redecode the instruction (in software), emulate the instruction,
and context change/state restore back to the virtual machine. in this
scenario ... the native hardware had additional support to directly
implement the instruction according to "virtual machine" rules. This
didn't involve executing the same operations faster ... this involved
the elimination of a lot of hypervisor overhead (state change in
and out of hypervisor kernel).

for other drift, old email from early 80s ... discussing the difference
between the SIE instruction implementation in 3081 and 3090
http://www.garlic.com/~lynn/2006j.html#email810630
in this post
http://www.garlic.com/~lynn/2006j.html#27 virtual memory


misc. past posts mentioning ECPS vm microcode assit:
http://www.garlic.com/~lynn/94.html#21 370 ECPS VM microcode assist
http://www.garlic.com/~lynn/94.html#27 370 ECPS VM microcode assist
http://www.garlic.com/~lynn/94.html#28 370 ECPS VM microcode assist
http://www.garlic.com/~lynn/2000.html#12 I'm overwhelmed
http://www.garlic.com/~lynn/2000c.html#50 Does the word "mainframe" still have a meaning?
http://www.garlic.com/~lynn/2000c.html#76 Is a VAX a mainframe?
http://www.garlic.com/~lynn/2000e.html#6 Ridiculous
http://www.garlic.com/~lynn/2000g.html#7 360/370 instruction cycle time
http://www.garlic.com/~lynn/2001i.html#2 Most complex instructions (was Re: IBM 9020 FAA/ATC Systems from 1960's)
http://www.garlic.com/~lynn/2001i.html#3 Most complex instructions (was Re: IBM 9020 FAA/ATC Systems from 1960's)
http://www.garlic.com/~lynn/2002e.html#75 Computers in Science Fiction
http://www.garlic.com/~lynn/2002l.html#51 Handling variable page sizes?
http://www.garlic.com/~lynn/2002l.html#62 Itanium2 performance data from SGI
http://www.garlic.com/~lynn/2002o.html#15 Home mainframes
http://www.garlic.com/~lynn/2002o.html#16 Home mainframes
http://www.garlic.com/~lynn/2002p.html#44 Linux paging
http://www.garlic.com/~lynn/2002p.html#48 Linux paging
http://www.garlic.com/~lynn/2003.html#4 vax6k.openecs.org rebirth
http://www.garlic.com/~lynn/2003.html#7 vax6k.openecs.org rebirth
http://www.garlic.com/~lynn/2003.html#14 vax6k.openecs.org rebirth
http://www.garlic.com/~lynn/2003.html#16 vax6k.openecs.org rebirth
http://www.garlic.com/~lynn/2003.html#17 vax6k.openecs.org rebirth
http://www.garlic.com/~lynn/2003.html#61 MIDAS
http://www.garlic.com/~lynn/2003d.html#21 PDP10 and RISC
http://www.garlic.com/~lynn/2003e.html#56 Reviving Multics
http://www.garlic.com/~lynn/2003f.html#21 "Super-Cheap" Supercomputing
http://www.garlic.com/~lynn/2003f.html#43 ECPS:VM DISPx instructions
http://www.garlic.com/~lynn/2003f.html#52 ECPS:VM DISPx instructions
http://www.garlic.com/~lynn/2003f.html#54 ECPS:VM DISPx instructions
http://www.garlic.com/~lynn/2003f.html#56 ECPS:VM DISPx instructions
http://www.garlic.com/~lynn/2003m.html#37 S/360 undocumented instructions?
http://www.garlic.com/~lynn/2004f.html#3 Infiniband - practicalities for small clusters
http://www.garlic.com/~lynn/2004f.html#21 Infiniband - practicalities for small clusters
http://www.garlic.com/~lynn/2004f.html#29 [Meta] Marketplace argument
http://www.garlic.com/~lynn/2004j.html#45 A quote from Crypto-Gram
http://www.garlic.com/~lynn/2004m.html#5 Tera
http://www.garlic.com/~lynn/2004q.html#64 Will multicore CPUs have identical cores?
http://www.garlic.com/~lynn/2004q.html#72 IUCV in VM/CMS
http://www.garlic.com/~lynn/2005d.html#41 Thou shalt have no other gods before the ANSI C standard
http://www.garlic.com/~lynn/2005d.html#59 Misuse of word "microcode"
http://www.garlic.com/~lynn/2005f.html#59 Where should the type information be: in tags and descriptors
http://www.garlic.com/~lynn/2005g.html#17 DOS/360: Forty years
http://www.garlic.com/~lynn/2005h.html#24 Description of a new old-fashioned programming language
http://www.garlic.com/~lynn/2005k.html#17 More on garbage collection
http://www.garlic.com/~lynn/2005k.html#38 Determining processor status without IPIs
http://www.garlic.com/~lynn/2005k.html#42 wheeler scheduler and hpo
http://www.garlic.com/~lynn/2005k.html#49 Determining processor status without IPIs
http://www.garlic.com/~lynn/2005k.html#50 Performance and Capacity Planning
http://www.garlic.com/~lynn/2005k.html#54 Determining processor status without IPIs
http://www.garlic.com/~lynn/2005k.html#59 Book on computer architecture for beginners
http://www.garlic.com/~lynn/2005n.html#12 Code density and performance?
http://www.garlic.com/~lynn/2005n.html#18 Code density and performance?
http://www.garlic.com/~lynn/2005n.html#45 Anyone know whether VM/370 EDGAR is still available anywhere?
http://www.garlic.com/~lynn/2005o.html#35 Implementing schedulers in processor????
http://www.garlic.com/~lynn/2005p.html#14 Multicores
http://www.garlic.com/~lynn/2005p.html#27 What ever happened to Tandem and NonStop OS ?
http://www.garlic.com/~lynn/2005p.html#29 Documentation for the New Instructions for the z9 Processor
http://www.garlic.com/~lynn/2005p.html#38 storage key question
http://www.garlic.com/~lynn/2005s.html#36 Filemode 7-9?
http://www.garlic.com/~lynn/2005u.html#40 POWER6 on zSeries?
http://www.garlic.com/~lynn/2005u.html#43 POWER6 on zSeries?
http://www.garlic.com/~lynn/2005u.html#44 POWER6 on zSeries?
http://www.garlic.com/~lynn/2005u.html#45 IBM's POWER6
http://www.garlic.com/~lynn/2006b.html#38 blast from the past ... macrocode
http://www.garlic.com/~lynn/2006c.html#11 Mainframe Jobs Going Away
http://www.garlic.com/~lynn/2006c.html#47 IBM 610 workstation computer
http://www.garlic.com/~lynn/2006j.html#21 virtual memory
http://www.garlic.com/~lynn/2006m.html#39 Using different storage key's
http://www.garlic.com/~lynn/2006m.html#54 DCSS
http://www.garlic.com/~lynn/2006n.html#44 Any resources on VLIW?
http://www.garlic.com/~lynn/2006o.html#23 Strobe equivalents
http://www.garlic.com/~lynn/2006r.html#37 REAL memory column in SDSF
http://www.garlic.com/~lynn/2006s.html#22 Why these original FORTRAN quirks?
http://www.garlic.com/~lynn/2006u.html#29 To RISC or not to RISC
http://www.garlic.com/~lynn/2006u.html#32 To RISC or not to RISC
http://www.garlic.com/~lynn/2006u.html#33 Assembler question
http://www.garlic.com/~lynn/2006u.html#34 Assembler question
http://www.garlic.com/~lynn/2006w.html#11 long ago and far away, vm370 from early/mid 70s
http://www.garlic.com/~lynn/2006y.html#21 moving on
http://www.garlic.com/~lynn/2007f.html#6 IBM S/360 series operating systems history
http://www.garlic.com/~lynn/2007f.html#14 more shared segment archeology
http://www.garlic.com/~lynn/2007f.html#16 more shared segment archeology
http://www.garlic.com/~lynn/2007g.html#72 The Perfect Computer - 36 bits?

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