Re: AMD announces SSE5 Instructions

Terje Mathisen wrote:

Klaus Fehrle wrote:
dave wrote:

http://developer.amd.com/assets/sse5_43479_BDAPMU_3-00_8-27-07.pdf


I wonder if these are all planned for implementation in CPU-Silicon
or a portion of it is intended to be processed on the GPGPU-part of
Fusion?

This is NOT Yet Another Instruction Set Extension: It is a totally
different/separate instruction set for integer & fp code, obviously
intended as a bridge between the GPU "Sea of FP units" and the
regular x86 core.

Nicely put. This is what i thought is needed and hoped the
instruction-set would provide. Would AMDs recently published initiative
http://developer.amd.com/LWP offer another perspective of looking at
this very same bridge iyo?

Regards
Klaus


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