Re: Canceled Niagara-like AMD project


In article <5amun6F2peiadU1@xxxxxxxxxxxxxxxxxx>,
"Del Cecchi" <delcecchiofthenorth@xxxxxxxxx> writes:
|> "Anton Ertl" <anton@xxxxxxxxxxxxxxxxxxxxxxxxxx> wrote in message
|> news:2007May12.201135@xxxxxxxxxxxxxxxxxxxxxxxxxxxxx
|> >
|> > The difference is that the posting gave the lack of sequential
|> > performance as the reason for canceling the project, whereas Anandtech
|> > reports power consumption issues and FB-DIMMs as reasons. I don't
|> > believe the FB-DIMM line, because the project was canceled in the
|> > concept stage, where the specific choice of RAM interface technology
|> > would have been easy to change.
|>
|> Unless you believe the commodity ram of the future is fbdimm so building
|> something that depends on that not being the case is foolish.

That is the converse of what the article said!

The nail in the coffin of AMD's ill fated project was its support
for FB-DIMMs. AMD quickly realized that Fully Buffered DIMM was not
going to come down in cost quickly enough in the near term to tie
its next microprocessor design to it. AMD eventually settled on
unbuffered and registered DDR2 instead of FBD.

AMD doubtless were hoping that they could increase the number of
FB-DIMM channels to several times that of DDR, because they need fewer
pins. But that wouldn't fly if they were too expensive.

The other key is in an earlier paragraph:

AMD overestimated the transition to multithreaded applications ...

The fact of the matter is that we aren't going to see much of a change
until we see a paradigm shift. Most of the currently threaded
applications could almost as easily (and rather more reliably) be
written as separate processes with a few shared memory segments. As
they often used to be. But only a few of those can make use of a lot
of CPUs, and even fewer can do so without concomitant memory bandwidth.

There are exceptions, but not all that many.


Regards,
Nick Maclaren.
.

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