Design Choice for MIPS implementation

Hey guys.. I am trying to implement a MIPS design which I learned a
few yrs ago in my undergrad days.

I pretty much have the entire design coded in verilog.

The closet thing to whats on my textbook (which I wrote the code for)
is below:
http://www.cs.ualberta.ca/~amaral/courses/429/webslides/Topic3-Pipelining/img008.jpg

I am trying to get the whole thing to run in just 1 cycle for
simplicity. For this reason, I only have the "program counter" (the
green "Address" register in the diagram) running on a clock edge. All
the other registers (instruction/data memories, register files, etc)
are triggered by their address/data/read/write inputs (and not by
clock). Is this the right approach? If not, how do I go about doing
this?

Thanks,

Mahurshi Akilla

.