multiprocessor system interconnected with AMBA?
- From: Sean <phixcoco@xxxxxxxxx>
- Date: 21 Apr 2007 01:27:56 -0700
Questions occured to my mind when i was reading AMBA spec 2.0 a few
days ago, and the primary issue came out of keeping cache coherency
between multiprocessors.
One problem is that if write INVALID is to be implemented, i find it
impossible to distinguish Read transactions from Read Exclusive
transaction, barely on signals given in AHB. if every Read transaction
is taken as Read Exclusive, there will be no Shared states, and that
would lose efficiency.
Another problem is that, if one processor confronts with read miss(a
Read transaction will be put on the bus) and a modified copy of the
data required is hitted in cache of another processor. how i hope that
i can transfer the copy from cache directly to requiring cache and
update memory simultanenously. however, it seems impossible under AHB
protocol. the only way i can find out is to retry previous transaction
and the hitted cache updates the memory, and previous transaction will
finish later when retries, then the right copy can be fetched from
memory!
I find that the only possible solution is read and write from memory,
no cache-to-cache transaction! That obviouly degrades the system
performance. is that out of intrinsic limitation of AMBA? or is there
solution to satisfy my requirements?
PS: im unfamiliar to ARM processor series, how to keep cache cohrency
if homogenous multiprocessor system is to be built using ARM
processors?
Any comment is welcomed!
thx!
Sean
.
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