Re: MIPS and RISC

On Apr 14, 7:33 pm, bina...@xxxxxxxxx wrote:
On Apr 14, 1:48 am, Joe Pfeiffer <pfeif...@xxxxxxxxxxx> wrote:





Eric Smith <e...@xxxxxxxxxxxx> writes:

MIPS has several meanings:

1. Millions of Instructions Per Second - an overly simplistic
benchmark measurement, also known as "Meaningless Indicator
of Processor Speed".

2. Stanford MIPS architecture, an academic RISC architecture (presumably
named based on the expansion above). Generally only of historical
interest, although some embedded processors from 8x8 and their
licensees use a derivative.

No -- the original MIPS paper made clear that the name was an acronym
for "Microprocessor without Interlocked Pipeline Stages", and had
nothing to do with the first defininition. To which the immediate
reaction was "pull the other one", of course.

3. MIPS architecture - a commercial RISC architecture based on (but not
identical to) the Stanford MIPS design.

4. MIPS Technologies is the company that developed the commercial
MIPS architecture and designs and license processor cores.

And, of course, at some point along the way they added interlocks
between the pipeline stages and it changed from MIPS to Mips (not an
acronym, just a word).

Some says MIPS to be "Microprocessor without Interlocked Pipeline
Stages", and some " Million instructions /second" .

In that case you mean , MIPS is a type of RISC architecture right ??

By the way, I tried to find some generic documents regarding MIPS
architecture like superscalar pipelining, branch prediction and so on
in net ( have tried mips.com too) but couldn't find any. Do anyof you
have some such documents. If you do, I will be highly thankful if you
can forward me.

Thanks a lot- Hide quoted text -

- Show quoted text -

"superscaler", "branch prediction" and so on are not specific to MIPS
architecture or even RISC. i personally recommended u refer to books
listed below:
"Modern Processor Design: Fundamentals of Superscalar Processors"
by John P. Shen
"Computer Architecture: A Quantitative Approach" by John L.
Hennessy and David A. Patterson

you can google those key words or even wiki contains some basic
information that might interest u.

Sean

.

Relevant Pages

  • Re: MIPS and RISC
    ... No -- the original MIPS paper made clear that the name was an acronym ... Some says MIPS to be "Microprocessor without Interlocked Pipeline ... MIPS is a type of RISC architecture right ?? ... I tried to find some generic documents regarding MIPS ...
    (comp.arch)
  • Re: mips and concurrency/simultaneous running tasks
    ... Scott Keogh wrote: ... > I was wondering if anyone can help me as im new to the mips architecture. ... architecture and minimal instruction set. ...
    (sci.electronics.basics)
  • Re: [Patch 01/12] Prepare the code for Hardware Breakpoint interfaces
    ... * Available values vary according to the architecture. ... I question weather having all these symbols for lengths is the proper approach. ... If we were to use a debug agent hooked into the MIPS EJTAG debugger ... in the arch-specific files and I don't see any part of the generic ...
    (Linux-Kernel)
  • Re: [RFC Patch 1/9] Introducing generic hardware breakpoint handler interfaces
    ... + * Available values vary according to the architecture. ... On MIPS we support breakpoint lengths that are powers of 2 between 8 and ... For architectures such as MIPS where a range of lengths can be possibly ... be specified in numeric terms to the kernel interface (say ...
    (Linux-Kernel)
  • Re: MIPS and RISC
    ... I am confused with the difference between MIPS and RISC ... MIPS is an architecture from this genré ... The first generation consisted of MIPS, SPARC, Motorola ... The second generation added HP PA-RISC, ALPHA, IBM Power, and mabe a ...
    (comp.arch)
Loading