Re: 21st Century ISA goals?

"ChrisQuayle" <nospam@xxxxxxxxxxxx> wrote in message news:K9cTh.1094$%K5.979@xxxxxxxxxxxxxxxxxxxxxxx
Haven't done any programming on pci, but if you have to fight
through several layers of hardware just to get to the device
register of interest, then yes, there could be timing penalties. It
also depends on whether the target controller is dma capable.
If you have to use programmed io, (read or write for every byte
or word transferred) for example, there would be a severe
speed penalty compared to a dma based transfer. As for cpu
resources, good drivers don't block other tasks while doing io.
A dma based driver sets up the controller with a few register
writes, kicks off the io, then returns control to the os. Only when
the io is complete does the controller issue a hardware interrupt to the driver, which then completes the transaction by signalling
the os. Under such conditions, % cpu time is pretty low.

I can understand why PIO would be considered evil, but after reading the description of how channel-based systems worked, I don't see much difference vs how modern DMA I/O works. You send off a command, return to normal processing, and get an interrupt when it's complete. The back-and-forth of cache lines to main memory is a problem, but I'd assume that Intel, AMD, et al have worked on ways around that since it's an obvious place to improve I/O performance and thus sell more chips.

The only major difference I see is that a channel-based system would have the "device driver" running on a different processor than the OS kernel runs on. Wouldn't syncing those two together cause just as much hassle as just running the device driver on the main CPU?

( I think I need to read more comparing and less explaining how each works in isolation... )

S

--
Stephen Sprunk "Those people who think they know everything
CCIE #3723 are a great annoyance to those of us who do."
K5SSS --Isaac Asimov


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