Re: Beyond multicore

In article <op.tou6cwnkm60l4k@xxxxxxxxxx>,
Ken Hagan <K.Hagan@xxxxxxxxxxxxxxxxxx> wrote:
On Wed, 07 Mar 2007 20:15:52 -0000, MitchAlsup <MitchAlsup@xxxxxxx> wrote:

We are reaching the point where silicon technology is enabling an
exponential increase in the number of cores on a die, but at best we
can expect a linear increase in the number of pins. So, pretty soon we
should feel the impact of hitting this brick wall at full speed......

Take away the pins used for the interconnect and dedicate them to DRAM
and that one-packaged-part system can support only 30 CPUs. Hardly a
way forward.

If the hardware can't avoid making some parts of "memory" run at
significantly different speeds (relative to any given processor), then it
might as well expose the difference and allow programmers to explicitly
partition problems between fast (on-chip, or as good as) storage (for
which 32-bit addressing might *always* be sufficient) and slow storage
(which, like IPv6 addressing, might benefit from a 128-bit address space
even if it never approaches 2**64 bytes in total size).

There are several problems in the marketplace that can benefit from
that solution. Video recoding, all audio transcoding, packet forwarding
and filtering, and some parts of video encoding all work on relatively
small amounts of data at any one time. Even a full IPv4 table fits
in L2 cache.

So option (D) is to back off the switch to 64-bit addressing, since what
is really needed is a mixed model with both 32-bit (near) and 128-bit
(far) pointers.

The fast memory only needs some tagging. A fast-mmap call to tell the
OS we want it, and fmalloc/ffree in user space.

Another alternative is to expose the difference to the OS, and let
the OS page between fast on-chip memory and DRAM paging space; and
use the exisiting code for locking in ram etc.

If the paging load of such a scheme is too great we can give the
processor a hardware assist similar to the one we have today in
cache handling.

-- mrr
.

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