Re: A way to speed up level 1 caches

nmm1@xxxxxxxxxxxxx (Nick Maclaren) writes:
Precisely. Whether that was so, I can't say. But it matched the
data I had, and is definitely a plausible hypothesis. It might
well be true today.

re:
http://www.garlic.com/~lynn/2007e.html#7 A way to speed up level 1 caches
http://www.garlic.com/~lynn/2007e.html#10 A way to speed up level 1 caches

one of the places where partitioned caches show benefit ... is
limiting the damage that some operation that has sequential/serial,
non-reuse pattern activity might have on other activity using the
cache (it wasn't that it improved good cache activity ... it just
bounded the effects of bad cache activity).

another "kernel" example has been tcp/ip stack kernel implementations.
some of the implementations have had large number of buffer copy
operations ... and w/o special non-caching support for data copies
.... easily wipes out any useful stuff in the cache(s) (especially when
dealing with larger buffer sizes). the processor cycles involved in
buffer copy cache effects can turn out to be larger than the processor
cycles involved in direct instruction execution.

one of the suggested benefits for posix asyncronous i/o ... besides
enabling various multi-threaded operations ... was being able to set
up direct i/o transfer into/out-of application space buffers ...
avoiding all buffer copy operations. this somewhat wanders into the
recent thread on multithreading
http://www.garlic.com/~lynn/2007d.html#61 ISA Support for Multithreading
http://www.garlic.com/~lynn/2007e.html#0 ISA Support for Multithreading
http://www.garlic.com/~lynn/2007e.html#8 ISA Support for Multithreading
.