Re: New Microprocessor architecture

Hi JonB,

I know that there are some dynamic reconfigurable systems. However,
they are not flexible enough to replace conventional CPU. The target of
my proposed architecture is to replace conventional CPU.

I suppose that PC run faster than FPGA only in some small programs. For
large programs like simulations, CAD, games which require a huge
computation load, PC should be slower than FPGA and FPGA should be
slower than ASIC. Actually, we want to enhance CPU performance for
applications which run in long time. For some applications which run in
only some seconds, it is not necessary to increase CPU performance.

The compiler for this architecture works differently from conventional
compiler. I first present here a little about the operation of this
arechitecture. This architecture is dataflow computer. In the dataflow
execution model, a program is represented by a directed graph. The
nodes of the graph are primitive instructions such as arithmetic or
comparison operations. The directed edges between nodes represent the
data dependencies between instructions. Output data of the previous
instruction is the input data of the next one. The data runs along the
edges in the queue way (First-In-First-Out). In order to avoid the data
hazard, people use tokens to determine the availability of input data.
Whenever all input edges of one node have tokens (all input data are
available), the node is said to be fireable. A fireable node removes
the tokens in the input edges, executes the instruction, places the
result with token into output edges, and waits to be fireable again. By
this method, instructions are schedule for execution as soon as their
operands become available.

With this approach, we do not use normal branch instructions like in
the von Neumann architecture. Instead, we have two specific
instructions "Branch" and "Merge". Branch node has two input
edges and two output edges. One input is used to control. If its data
is "true" or "false", branch node moves data from the rest
input edge to the first or second output edge respectively. Merge node
has three input edges and one output edge. One input is used to
control. If its data is "true" or "false", merge node moves
data from the second or third input edge to the output edge
respectively.

The key advantage of this model is that, in dataflow, more than one
instruction can be executed at once. Thus, if several instructions
become fireable at the same time, they can execute in parallel. In this
approach, detecting data dependencies can be done easily by checking
tokens (we do not have to rename, forward...), control dependencies
come into data dependencies by using "Branch" and "Merge" (we
do not have to predict). Therefore, it may be possible to exploit the
whole potential of ILP easily.

The compiler for this architecture works in the following way. Firstly,
it creates a dataflow graph for instruction within loops. It is similar
to compilers for dataflow computer which was common in 80s. Sencondly,
it maps this graph to the 2D array of processing elements (similar to
FPGA). One primitive operation coresponses to one processing element.
Each processing element has one unique address (in a network). The
instruction for this element has its address.

When running, program counter first broadcast instructions to network.
Processing elements get their instructions base on the address. After
that they fetch instruction into data path to create a dataflow graph
and process. This structure process data in flow and similarly to FPGA
manner.

Nguyen.

.

Relevant Pages

  • RE: z/OS on the ISERIES
    ... "Although the System/360 architecture was originally designed to support ... Instructions and data formats of the architecture are for the most part ... EBCDIC, not the zSeries hardware. ... Subject: z/OS on the ISERIES ...
    (bit.listserv.ibm-main)
  • Re: 10 bit per channel YUV with alpha
    ... Aren't those, like, Pentium specific details which aren't really relevant anymore..? ... Intel has like 3 major architecture designs since then for implementing the IA32.. ... Then AMD has their own architecture, which again doesn't benefit much if at all from pairing instructions in specified manner. ... memory read requests can create arbitrary bottlenecks and dependencies.. ...
    (microsoft.public.win32.programmer.directx.video)
  • Re: [NEWBIE] i686 architecture
    ... > met with RISC and CISC architectures), ... Though those manuals are for the Pentium 4, the architecture is largely the ... eax - accumulator reg; usually encodes shorter than other instructions; used ... any register can be used in a general-purpose fashion. ...
    (comp.lang.asm.x86)
  • Re: Why was VAX abandonned ?
    ... Antonio Carlini wrote: ... > the major mover to get byte loads/stores into the architecture. ... > been such a huge mistake, someone would surely have spotted it (the ... > these instructions would cause a performance issue for some people, ...
    (comp.os.vms)
  • Re: Why was VAX abandonned ?
    ... Antonio Carlini wrote: ... > the major mover to get byte loads/stores into the architecture. ... > been such a huge mistake, someone would surely have spotted it (the ... > these instructions would cause a performance issue for some people, ...
    (comp.os.vms)