P4-Chipset-Question

I've got a question regarding P4-Chipsets: The P4 has a cacheline-length
of 128 Bytes in the L2-Cache, i.e. 16 * 64 bits and the largest SDRAM-Burst
below a full page burst is 8X, i.e. 8 * 64 bits on a standard-DIMM. So it's
the best to decrease latency by loading a cacheline by two parallel bursts
from both channels. This would it make possible to share the address-lines
of both channels and as they're clocked with half the clockspeed of the
bursts, this would be possible - is this implemented by some or most of
the P4-chipsets (all chipsets isn't possible because there is at least
one that supports the Core-2).
But under this circumstances, the latency of the P4 SDRAM-access would
be comparable to the latency of Athlon-chipsets (Socket-A) which support
the same SDRAM-clocking. But the numbers I've seen are higher by about
50%. So is this parallel-burst-feature not implemented by any chipset?
Maybe because it's more worth to be capable of having the opportunity
to do two independent operations in parallel on both channels?
And Ih heard the reason for the long cacheline-length of the P4 is that
it is was designed for Rambus-RIMMs; can anyone explain this for me which
features of RIMMs make 128 byte cachelines preferrable?
.

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