Re: Uncached memory access...

Doug MacKay wrote:
Roy L Butler wrote:
Hi,

When mapping or otherwise accessing main memory in an uncached manner,
say for reading from a device, I understand it bypasses cache hits and
reads directly from the memory referenced, but as the reads are
fulfilled, do they then populate the cache? If so, is there a way
around this? Specifically, I'm interested in reading data from a media
stream that I don't want to fill the cache, as it will never be referred
to a second time. I was in a Cell processor presentation where they
mentioned this could be done and am interested if this is a common
feature or "special" to their platform.


Thanks all,
Roy

Its relatively common.

In x86 (and I believe CBE but I haven't dug into its cores much) you
can mark memory regions as uncacheable. The caches are aware of this
page attribute and will not store the data locally on reads or writes
(though you may encounter write-combining of uncacheable addresses).

Another feature that you may want to look at for what you're doing are
the media instructions in place on many cores. Most of these media
extensions include non-cacheable read and write instructions.

I'd recommend taking a look at the architectural programmer's manual
for the cores you're targeting. There should be pages and pages of
information on this.


Thanks for the good info. I'll check out the architectural programmer's manuals of specific CPUs I'm interested in.


Roy
.

Relevant Pages

  • Re: Cached memory never gets released
    ... Stock linux 2.4.26 kernel. ... Due to flash bug 3M of memory gets lost due to font memory getting lost ... The output of "free" cache number steadily grows. ... longer to exhaust all of system memory with the cache. ...
    (Linux-Kernel)
  • Re: Problem: Creating a raw binary string
    ... > While its true that a 64-bit cpu will move twice the data per instruction it ... > Memory bus width plays an important role here and unless it too is widened / ... You are forgetting the two levels of cache in the processor. ... The memory chips are addressed in Row col fashion. ...
    (alt.comp.lang.borland-delphi)
  • Re: Is Greenspun enough?
    ... Most OSes memory map executables directly from the file system so code doesn't pollute the file cache or swap space. ...
    (comp.lang.lisp)
  • Re: Superstitious learning in Computer Architecture
    ... Without a LOT of logic or some other better approach, re-executing the instructions requires re-decoding and it ties up the cache memory bus transferring more data as instructions than the instructions are working on. ... The concept of cache is fundamentally flawed in that it STILL restricts access to one word per clock cycle, when a single modern ALU can easily use 5 plus whatever is eaten up with instruction accesses. ... The size of an optimizing compiler is proportional to the SQUARE of the size of the language times the SQUARE of the complexity of the machine - because all interactions must be considered. ...
    (comp.arch.arithmetic)
  • Re: FPGA-based hardware accelerator for PC
    ... I know that in most cases the CPU ... that it contsins no cache, as BRAMs are too precious resources to be wasted ... The BRAMs are what define the opportunity, ... many threads with full associativity of memory lines using hashed MMU ...
    (comp.arch.fpga)
Loading