Re: Need a Atomic function for Mips 4000c

"Eric P." wrote:

There is also an anti-ping-pong mechanism so that if two processors
both do a LL/SC at the same instant, one is guaranteed to succeed.

I found a description in the 21264 manual.
There is no lock register or anti-ping-pong gadget (hmmm, I thought
I remembered reading something about that. Oh well...).

In summary (glossing over a bunch of gotchas):
The LDx_L just does a normal cache line read (possibly shared state).
The STx_C tests the line state. If it is invalid, the store fails.
If it is valid but clean, it attempts to take ownership of the
line and transition to a dirty state (and invalidate any copies).
If it succeeds in changing to a dirty state, it temporarily locks
the cache line and the store succeeds, otherwise the store fails.
If another processor performs a intervening write, the line
transitions to an invalid state and the store fails.

Eric

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