Re: Need a Atomic function for Mips 4000c


"Jan Vorbrüggen" <jvorbrueggen-not@xxxxxxxxxxx> wrote in message
news:4bbaheF10jc6cU1@xxxxxxxxxxxxxxxxx
On EV6 and later, the LDL sets a per-processor flag which is cleared by
*any* memory write on the processor. The STC checks this flag to
determine
if something changed on the local processor (this handles the interrupts
and
traps conditions),

...with the important implication (I know that you know that, Fred) that
your
locking code is not allowed to execute any writes between the LL and the
SC.
That's a significant restriction that broke quite some code when the EV6
was
introduced, didn't it, Fred?


I woudn't say "quite some code" but yes, there was some generated LDL/STC
code sequences out there that were broken and we supplied an application
that could look through the binary images to detect them (so they could be
fixed).\


.