Re: Need a Atomic function for Mips 4000c

"The Alpha and MIPS 4000 processor architectures have no atomic
read-modify-write instructions, i.e., no test-and-set-lock instruction
(TS). Atomic update is supported by pairs of load_locked (LDL) and
store-conditional (STC) instructions.

The semantics of the Alpha architecture\u2019s LDL and STC
instructions are as follows. Executing an LDL Rx, y instruction loads
the memory at the specified address (y) into the specified general
register (Rx), and holds y in a special per-processor lock
register. STC Rx, y stores the contents of the specified gen- eral
register (Rx) to memory at the specified address (y), but only if y
matches the address in the CPU\u2019s lock register. If STC succeeds,
it places a one in Rx; if it fails, it places a zero in Rx. Several
kinds of events can cause the machine to clear the CPU lock register,
including traps and interrupts. Moreover, if any CPU in a
multiprocessor system successfully completes a STC to address y, then
every other pro- cessor\u2019s lock register is atomically cleared if
it contains the value y."

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