comp.arch

Thread Index

Re: Return address stack
- From: robertwessel2@xxxxxxxxx
Re: Disadvantages and advantages of condition code register and general-purpose register
- From: Terje Mathisen
Re: Regarding address bus
- From: Del Cecchi
Return address stack
- From: Peter
Re: Vectored Interrupt Fetch
- From: Seongbae Park
Re: Regarding address bus
- From: MitchAlsup
Re: Vectored Interrupt Fetch
- From: John Mashey
Re: Disadvantages and advantages of condition code register and general-purpose register
- From: robert . thorpe
Regarding address bus
- From: sam_cit
Regarding address bus
- From: sam_cit
Re: Vectored Interrupt Fetch
- From: Jan Vorbrüggen
CFP - IEEE ICICIC2006 Special Session on Integrated Control and Computing
- From: CoupeXia
Re: Disadvantages and advantages of condition code register and general-purpose register
- From: Andy Glew
Re: Vectored Interrupt Fetch
- From: Eric P.
Re: Disadvantages and advantages of condition code register and general-purpose register
- From: robert . thorpe
Re: Vectored Interrupt Fetch
- From: Niels Jørgen Kruse
Re: Vectored Interrupt Fetch
- From: Peter Dickerson
Re: Vectored Interrupt Fetch
- From: Jan Vorbrüggen
Re: Disadvantages and advantages of condition code register and general-purpose register
- From: Eric P.
Re: Harvard Vs Von Neumann architecture
- From: rambam
Re: Harvard Vs Von Neumann architecture
- From: fox
Re: AlphaStation 200
- From: toby
Re: AlphaStation 200
- From: Bob McConnell
Re: AlphaStation 200
- From: toby
AlphaStation 200
- From: Bob McConnell
Re: Disadvantages and advantages of condition code register and general-purpose register
- From: Niels Jørgen Kruse
Re: Vectored Interrupt Fetch
- From: windenntw@xxxxxxxxx
Re: Harvard Vs Von Neumann architecture
- From: Alex Gibson
Re: Harvard Vs Von Neumann architecture
- From: Eric Smith
Re: Comp.arch and RWT dinner Monday the 6th during ISSCC
- From: Eugene Miya
Re: send more than 8 bits with parallel port?
- From: Terje Mathisen
Re: Vectored Interrupt Fetch
- From: MitchAlsup
Re: send more than 8 bits with parallel port?
- From: Terje Mathisen
Re: The Fastest CPU
- From: Eugene Miya
Re: hpux11 PA-RISC ABI Specification
- From: Cary Coutant
Vectored Interrupt Fetch
- From: Robert Finch
Re: Disadvantages and advantages of condition code register and general-purpose register
- From: Eric P.
Re: 64 bit humour
- From: John F. Carr
Re: Disadvantages and advantages of condition code register and general-purpose register
- From: Niels Jørgen Kruse
Re: send more than 8 bits with parallel port?
- From: Joe Pfeiffer
Re: Disadvantages and advantages of condition code register and general-purpose register
- From: Eric P.
Re: Flat segments optimized on x86?
- From: MitchAlsup
Re: Flat segments optimized on x86?
- From: Eric Northup
Re: Flat segments optimized on x86?
- From: Andy Glew
Flat segments optimized on x86?
- From: Udo A. Steinberg
64 bit humour
- From: Robert Finch
Re: Dual Core CPU vs Dual PHYSICAL CPUs
- From: Rick Jones
Re: Dual Core CPU vs Dual PHYSICAL CPUs
- From: physicsboy
Re: A Historical Look at the VAX
- From: Anne & Lynn Wheeler
Re: Disadvantages and advantages of condition code register and general-purpose register
- From: Eric P.
A Historical Look at the VAX
- From: Grumble
Re: send more than 8 bits with parallel port?
- From: robertwessel2@xxxxxxxxx
Re: send more than 8 bits with parallel port?
- From: Andrew Reilly
Re: send more than 8 bits with parallel port?
- From: David Hopwood
Re: Dual Core CPU vs Dual PHYSICAL CPUs
- From: David Hopwood
Re: Dual Core CPU vs Dual PHYSICAL CPUs
- From: Silvius Rus
send more than 8 bits with parallel port?
- From: jccorreu@xxxxxxxxx
Re: Dual Core CPU vs Dual PHYSICAL CPUs
- From: physicsboy
Re: Harvard Vs Von Neumann architecture
- From: Grumble
Re: Harvard Vs Von Neumann architecture
- From: MitchAlsup
Re: Dual Core CPU vs Dual PHYSICAL CPUs
- From: MitchAlsup
Re: Harvard Vs Von Neumann architecture
- From: Anne & Lynn Wheeler
Re: Searching for explanations on the way a processor works
- From: Del Cecchi
Dual Core CPU vs Dual PHYSICAL CPUs
- From: physicsboy
Re: hp c8000 windows ??
- From: Knife&Fork
hp c8000 windows ??
- From: olivier . serrano
Re: Good Books on CPU Architecture
- From: Ranjit Mathew
Re: Harvard Vs Von Neumann architecture
- From: Del Cecchi
Re: virtualization?
- From: Anne & Lynn Wheeler
Re: virtualization?
- From: Wes Felter
Re: Searching for explanations on the way a processor works
- From: TC
Re: Harvard Vs Von Neumann architecture
- From: CJT
Re: Searching for explanations on the way a processor works
- From: Nicolas
Re: Disadvantages and advantages of condition code register and general-purpose register
- From: Andrew Reilly
Re: Harvard Vs Von Neumann architecture
- From: Patrick Schaaf
Harvard Vs Von Neumann architecture
- From: priyasmita_guha@xxxxxxxxxxx
Re: Disadvantages and advantages of condition code register and general-purpose register
- From: Mark Smotherman
Re: Searching for explanations on the way a processor works
- From: Paul Pluzhnikov
Re: Searching for explanations on the way a processor works
- From: Stephen Fuld
Searching for explanations on the way a processor works
- From: Nicolas
Re: Parallelism in an IAS computer
- From: hansp
Parallelism in an IAS computer
- From: priyasmita_guha@xxxxxxxxxxx
Re: Disadvantages and advantages of condition code register and general-purpose register
- From: Andy Glew
Re: Disadvantages and advantages of condition code register and general-purpose register
- From: Niels Jørgen Kruse
Re: Disadvantages and advantages of condition code register and general-purpose register
- From: Dysthymicdolt
Re: Disadvantages and advantages of condition code register and general-purpose register
- From: Dysthymicdolt
Re: Disadvantages and advantages of condition code register and general-purpose register
- From: Dysthymicdolt
Re: Disadvantages and advantages of condition code register and general-purpose register
- From: Andy Freeman
virtualization?
- From: jamesnathanjones
Re: static vs dynamic scheduling
- From: Niels Jørgen Kruse
Re: Disadvantages and advantages of condition code register and general-purpose register
- From: Torben Ægidius Mogensen
Re: Good Books on CPU Architecture
- From: physicsboy
Re: Good Books on CPU Architecture
- From: ada_student
Re: Disadvantages and advantages of condition code register and general-purpose register
- From: Dysthymicdolt
Re: Good Books on CPU Architecture
- From: Grumble
Good Books on CPU Architecture
- From: physicsboy
Re: Disadvantages and advantages of condition code register and general-purpose register
- From: Eric P.
Re: Disadvantages and advantages of condition code register and general-purpose register
- From: Seongbae Park
static vs dynamic scheduling
- From: ada_student
Re: Disadvantages and advantages of condition code register and general-purpose register
- From: Seongbae Park
Re: Architectural support for programming languages
- From: nituteodor
ok
- From: nituteodor
ok
- From: nituteodor
Re: Architectural support for programming languages
- From: nituteodor
Re: Disadvantages and advantages of condition code register and general-purpose register
- From: Torben Ægidius Mogensen
Re: Disadvantages and advantages of condition code register and general-purpose register
- From: Dennis M. O'Connor
Re: Disadvantages and advantages of condition code register and general-purpose register
- From: Stephen Fuld
Re: Disadvantages and advantages of condition code register and general-purpose register
- From: Andrew Reilly
Re: Disadvantages and advantages of condition code register and general-purpose register
- From: Iain McClatchie
Re: Disadvantages and advantages of condition code register and general-purpose register
- From: Peter L. Montgomery
Re: Disadvantages and advantages of condition code register and general-purpose register
- From: Stephen Fuld
Re: Disadvantages and advantages of condition code register and general-purpose register
- From: Joe Seigh
Re: Disadvantages and advantages of condition code register and general-purpose register
- From: Torben Ægidius Mogensen
Re: Disadvantages and advantages of condition code register and general-purpose register
- From: Anton Ertl
Re: Disadvantages and advantages of condition code register and general-purpose register
- From: Patrick Schaaf
Re: Disadvantages and advantages of condition code register and general-purpose register
- From: David Kanter
Re: Disadvantages and advantages of condition code register and general-purpose register
- From: Torben Ægidius Mogensen
Re: Disadvantages and advantages of condition code register and general-purpose register
- From: Torben Ægidius Mogensen
Re: Disadvantages and advantages of condition code register and general-purpose register
- From: Torben Ægidius Mogensen
Re: Disadvantages and advantages of condition code register and general-purpose register
- From: Nudge
Re: C++: 64 bit performance vs. 32 bit
- From: Andy Freeman
Re: garbage collection and page zeroing (was: Architectural ...)
- From: Andy Glew
Re: C++: 64 bit performance vs. 32 bit
- From: Andy Glew
Re: C++: 64 bit performance vs. 32 bit
- From: Anton Ertl
Re: C++: 64 bit performance vs. 32 bit
- From: Brian Hurt
Re: C++: 64 bit performance vs. 32 bit
- From: Andy Glew
Re: Disadvantages and advantages of condition code register and general-purpose register
- From: Andy Glew
garbage collection and page zeroing (was: Architectural ...)
- From: Anton Ertl
Re: C++: 64 bit performance vs. 32 bit
- From: Andy Freeman
Re: C++: 64 bit performance vs. 32 bit
- From: Anton Ertl
Re: Architectural support for programming languages
- From: Peter L. Montgomery
Re: C++: 64 bit performance vs. 32 bit
- From: Andy Glew
Re: Disadvantages and advantages of condition code register and general-purpose register
- From: Joe Seigh
Re: Disadvantages and advantages of condition code register and general-purpose register
- From: Torben Ægidius Mogensen
Re: Architectural support for programming languages
- From: Torben Ægidius Mogensen
Re: Disadvantages and advantages of condition code register and general-purpose register
- From: Jan Vorbrüggen
Re: Disadvantages and advantages of condition code register and general-purpose register
- From: Niels Jørgen Kruse
Re: Disadvantages and advantages of condition code register and general-purpose register
- From: robert . thorpe
Re: Disadvantages and advantages of condition code register and general-purpose register
- From: robertwessel2@xxxxxxxxx
Re: MOESI protocol
- From: Wei
Re: Architectural support for programming languages
- From: Anne & Lynn Wheeler
Re: Architectural support for programming languages
- From: JJ
Re: Architectural support for programming languages
- From: JJ
Re: Disadvantages and advantages of condition code register and general-purpose register
- From: MitchAlsup
Re: MOESI protocol
- From: MitchAlsup
Re: Architectural support for programming languages
- From: Jan Vorbrüggen
Re: Architectural support for programming languages
- From: Ketil Malde
Re: Architectural support for programming languages
- From: Joe Seigh
Re: spice model
- From: Del Cecchi
Re: Architectural support for programming languages
- From: john Doef
Re: Architectural support for programming languages
- From: Joe Seigh
Re: Architectural support for programming languages
- From: Torben Ægidius Mogensen
Re: Architectural support for programming languages
- From: john Doef
Re: Architectural support for programming languages
- From: Jan Vorbrüggen
Re: Architectural support for programming languages
- From: Anton Ertl
Re: Architectural support for programming languages
- From: Torben Ægidius Mogensen
Re: spice model
- From: David Kanter
spice model
- From: junaid
Re: Disadvantages and advantages of condition code register and general-purpose register
- From: boytx
Re: Disadvantages and advantages of condition code register and general-purpose register
- From: Mayank Kaushik
Re: MOESI protocol
- From: Joe Pfeiffer
Re: Disadvantages and advantages of condition code register and general-purpose register
- From: Joe Pfeiffer
MOESI protocol
- From: Wei
Re: C++: 64 bit performance vs. 32 bit
- From: Bernd Paysan
Re: Disadvantages and advantages of condition code register and general-purpose register
- From: mihir
Re: Disadvantages and advantages of condition code register and general-purpose register
- From: Mayank Kaushik
Disadvantages and advantages of condition code register and general-purpose register
- From: mihir
Re: C++: 64 bit performance vs. 32 bit
- From: Andy Glew
Re: Architectural support for programming languages
- From: fox
Re: C++: 64 bit performance vs. 32 bit
- From: Grumble
Re: C++: 64 bit performance vs. 32 bit
- From: Niels Jørgen Kruse
Re: C++: 64 bit performance vs. 32 bit
- From: Brian Hurt
Re: Architectural support for programming languages
- From: Robert Swindells
Re: Architectural support for programming languages
- From: Peter \"Firefly\" Lund
Re: Architectural support for programming languages
- From: Niels Jørgen Kruse
Re: Architectural support for programming languages
- From: Xavier Leroy
Re: Architectural support for programming languages
- From: Anton Ertl
Re: Architectural support for programming languages
- From: Nudge
Re: Architectural support for programming languages
- From: Peter \"Firefly\" Lund
Re: Any motherboards that support ONLY latest technologies?
- From: TimOnGoogle
Re: Comp.arch and RWT dinner Monday the 6th during ISSCC
- From: Eugene Miya
Re: RFC 2988 - how relevant in modern practice?
- From: already5chosen
Re: Architectural support for programming languages
- From: Peter \"Firefly\" Lund
Re: Architectural support for programming languages
- From: Anton Ertl
Re: Any motherboards that support ONLY latest technologies?
- From: Anton Ertl
Re: Architectural support for programming languages
- From: Bernd Paysan
Re: Any motherboards that support ONLY latest technologies?
- From: Rob Warnock
Re: RFC 2988 - how relevant in modern practice?
- From: glen herrmannsfeldt
Re: Architectural support for programming languages
- From: glen herrmannsfeldt
Re: Architectural support for programming languages
- From: Peter \"Firefly\" Lund
Architectural support for programming languages
- From: Mayank Kaushik
Multi-Cores and power consumption (was: Would multi-core replace SMPs?)
- From: Anton Ertl
Re: Would multi-core replace SMPs?
- From: Joe Seigh
Re: Would multi-core replace SMPs?
- From: Ketil Malde
Re: Would multi-core replace SMPs?
- From: already5chosen
Re: Would multi-core replace SMPs?
- From: Del Cecchi
Re: Numalink/Numaflex and Power5 Cache Designs
- From: Del Cecchi
Re: Would multi-core replace SMPs?
- From: Joe Seigh
Looking for the right 8051 to use on your next project ?
- From: Chris Stephens
Numalink/Numaflex and Power5 Cache Designs
- From: Michael E. Thomadakis
Re: RFC 2988 - how relevant in modern practice?
- From: Rick Jones
Re: Would multi-core replace SMPs?
- From: Gabriel Loh
Re: RFC 2988 - how relevant in modern practice?
- From: already5chosen
Re: RFC 2988 - how relevant in modern practice?
- From: Grumble
RFC 2988 - how relevant in modern practice?
- From: already5chosen
Re: Would multi-core replace SMPs?
- From: Jan Vorbrüggen
Re: Would multi-core replace SMPs?
- From: Anne & Lynn Wheeler
Re: Would multi-core replace SMPs?
- From: Andy Glew
Re: Would multi-core replace SMPs?
- From: John Mashey
Re: C++: 64 bit performance vs. 32 bit
- From: Stephen SM WONG
Re: Caches Access cost
- From: Jonathan Thornburg -- remove -animal to reply
Re: C++: 64 bit performance vs. 32 bit
- From: Christoph Breitkopf
C++: 64 bit performance vs. 32 bit
- From: schouwla
Tuesday Night RWT & Comp.arch Dinner, 7:30 at SF Marriott
- From: David Kanter
Re: Comp.arch and RWT dinner Monday the 6th during ISSCC
- From: Rob Warnock
Re: Comp.arch and RWT dinner Monday the 6th during ISSCC
- From: Iain McClatchie
Re: Comp.arch and RWT dinner Monday the 6th during ISSCC
- From: David Kanter
Re: hpux11 PA-RISC ABI Specification
- From: Richard
Re: Problem building Wattch 1.02 on Linux
- From: Lower Power
Re: Comp.arch and RWT dinner Monday the 6th during ISSCC
- From: David Kanter
Re: Comp.arch and RWT dinner Monday the 6th during ISSCC
- From: Eugene Miya
Re: hpux11 PA-RISC ABI Specification
- From: Grumble
Comp.arch and RWT dinner gathering during ISSCC
- From: David Kanter
Re: Problem building Wattch 1.02 on Linux
- From: Krishnan
Call for Papers: IAENG International Workshop on Scientific Computing and Computational Statistics (in IMECS 2006)
- From: imecs__2006
Problem building Wattch 1.02 on Linux
- From: Lower Power
Re: free to implement modern isa?
- From: Andrew Reilly