Re: Intel strikes back with a parallel x86 design
- From: MitchAlsup@xxxxxxx
- Date: 23 Sep 2005 11:56:53 -0700
Jim Brooks wrote:
> Stevel Jobs does a 180' and enthusiastically becomes
> Intel's bedfellow on the basis of a compelling roadmap.
> That roadmap has to be pretty darned interesting.
Only in comparison to PowerPC roadmaps.....
> Intel claims they aren't developing Hyperthreading anymore.
Perhaps they understand the costs and benefits better now.
> My speculation is that Intel will build on their HyperThread experience
> to design a "parallel x86". x86 CPUs have become superscalar machines.
> The next evolutionary step is a parallel machine. Dual-cores are only
> an inefficient stop-gap design that wastes transistors with duplicated
> or unnecessary resources (eg coherency logic between the core's caches).
Actually, a dual core chip is more efficient than a hyperthreaded chip
in terms of delivering performance to applications and especially so
when a power limit is imposed. A hyperthreaded P4 gets (lets just say)
25% more performance than its unithreaded version; whereas a dual core
chip gets closer to 75% more performance than a unithreaded version.
Now if the dual core chip is small enough to yield well; it wins!
> My ideas for a parallel x86:
> - thread quantums
> - thread prioritization
> - sub-threads
> - thread exceptions
> - cache lines have thread bits in addition to LRU bits
All these complicated additions to support an abandoned evolutionary
path
And there is still no high performance means to synchronize these
cooperating multiple tasks...And by high performance I mean
bigO(ln(n)); not the current bigO(n**3) typical (with worst case of
NP-complete if the timing is just right).
> - ALUs: 8 simple, 4 complex.
>
> - FPUs: 4 FADD, 4 FMUL, 2 FLDST.
What give you the idea that this would outperform 4 simpler cores that
are even less superscalar than current architectures (with the same
on-die cache hierarchy)?
> - deprecation of FP SIMD instruction set
Never happen, in fact, I suspect just the opposite! SSE will be
enhanced for new purposes such as (//pure speculation mode = on) A)
Fixed point Decimal, B) Floating Point Decimal, C) 128-bit binary
Floating point, or D) various 3D graphics computations.
.
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