Re: AMBA bus (rev.2, 1999) test support architecture
- From: m_bocchi@xxxxxxxxx
- Date: 13 Sep 2005 14:42:41 -0700
I've been working with AMBA 2.0 for the last 2 years.
I personally developed the bus architecture and a Test Interface
Controller followin the AMBA specification.
The TIC provides a support for testing all the slaves on the bus. It is
a bus master that can operate like any other master, but is controlled
from an external bus interface (EBI). This means that it has no way to
access to internal cores if you don't provide a slave interface to what
you need to read/write. It is a substitute of the microcontroller on
If you are considering to insert any DFT support, AMBA does not
standardize DFT structures and you should insert this hardware by your
But if your system is quite complex it is convenient to include also
the TIC if you want to test each peripheral from the AHB/APB bus.
I successfully run some tests using an Agilent pattern generator and a
logic state analyzer on a prototype chip, testing memories and
Hope I answered your question.
> I realize that AMBA bus interface provides some test support. It has
> the Test Interface Controller (TIC) which can interface to the ATE.
> But what I'm wondering is, does the test architecture as defined in the
> AMBA specification (rev.2) provide the mechanism to apply the test
> vectors to the cores?
> If yes, what kind of DFT does it support?
> If not, does it mean that all the required DFT (scan chain, wrapper,
> TAM, etc) has to be included by the test engineer?
> Hope you can share your knowledge and experience using AMBA bus
> Thank you in advance,
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