Re: stalling the TSC?


In article <daudul$dlh$1@xxxxxxxxxxxxxxxxxxxxxxx>,
Terje Mathisen <terje.mathisen@xxxxxxxxxxxxx> writes:
|> Nick Maclaren wrote:
|> > In article <p73d5ptpcip.fsf@xxxxxxxxxxxxx>,
|> > Andi Kleen <freitag@xxxxxxxxxxxxxxxxxx> wrote:
|>
|> >>Look up HPET. It's pretty modern and mostly usable with only minor
|> >>warts. Unfortunately many x86 vendors don't enable it yet (even when
|> >>the chipset has it in theory) because the current versions of Windows
|> >>don't use it and they don't enable anything that's not used by
|> >>Windows. This leaves other timers which have various problems, but can
|> >>be still used with some performance penalty.
|> >
|> > Thanks. I will look at it and see if anyone is learning anything
|> > from experience, even if not history :-)
|>
|> I believe I wrote a post about this, it still has several stupid warts,
|> some of which could have made it much more useful if avoided. :-(

A brief look at it indicates that it has more warts that Oliver
Cromwell, and addresses only a small part of the problem. It may
be better than what was there before, but it is still ghastly.
Consider the following 'minor' issues:

Real-time accuracy, including resynchronisation after coming
out of S1 and S2 (sleep?) states. Like, none.

Maintaining consistency across SMP systems. Like, none.

Integrating it with any 'GHz' timer (i.e. a cycle counter).
Like, none.

500 ppm? And only for periods of over 1 mS? And the wording
is such that it is allowed to be be 18,000 ppm out for intervals
of just over 100 uS :-)

I like femptoseconds - clearly a short interval with no content.


Regards,
Nick Maclaren.
.

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