Re: clock enable for fixed interval
- From: Marc Jet <jetmarc@xxxxxxxxxxx>
- Date: Fri, 16 Sep 2011 09:09:07 -0700 (PDT)
Your approach is flawed. It will not work well because it is not in
line with the generally accepted way of FPGA programming. It uses
asynchronous logic, which is frowned upon because the tools don't
support it well. Insisting on using asynchronous logic will do you no
favor.
It's perfectly valid that you want a clock-enable. However, it's
unusual that you want the clock-enable to be centered "around the
clock edge". It probably stems from working with discrete chips, where
THAT was most reliable way to enable clocks.
In logic (discrete or FPGA), it's also possible to "enable" clocks by
adding the enable as extra logic input, plus feedback of the previous
output. Then you can "always clock" the register, yet make it only
accept (honor) the change when "enable" is active. From the logic
point of view, this is equivalent to a real clock-enable. But from
other points of view, like for example power consumption, it may not
be.
Yet it is good enough, and it helps achieving another goal: make a
whole design from nothing but synchronous logic! This has been a
major milestone in FPGA architecture. It's so much easier to do timing
analysis on purely synchronous designs. In fact, the current tools do
almost exclusively synchronous analysis ("static timing"). It was
easier to make designs synchronous, than to make the tools handle
asynchronous designs..
Using synchronous logic is very important for you. If you have any
timing problems with your design, then you've either not read the
timing report, or you've used non-synchronous tricks and are about to
regret them.
Your desire to enable clocks is very wide spread, and so the FPGA
makers have implemented support for their synchronous equivalent,
right in the hardware. The necessary extra logic input and the
feedback of the previous state is "free" in all modern (and not so
modern) FPGAs. There is dedicated circuitry just for this purpose.
The following code shows how to register something on every other
cycle. The tools will recognize it and use none of "your" resouces
for it.
process (clk)
begin
if rising_edge(clk) then
clkenable <= not(clkenable);
end if;
end process;
process (clk)
begin
if rising_edge(clk) then
if clkenable='1' then
reg_something <= combinatorial_something;
end if;
end if;
end process;
PS: There is another common desire for asynchronous logic in many
designs, specifically for RESET. Read about it in other threads on
this group or elsewhere. There's more opinion about it because doing
it wrong doesn't fail right away. Yet (in my opinion) you should also
go strictly synchronous because that's what the tools can handle.
.
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