Re: Scoping a glitch

First is the input to the NEXYS2 IO connector pin, driven by a TI
ISO7240c chip, with about a 150 series resistor. This shows an
incidence where the counter incorrectly counted on the falling edge:

What's the signal path to the FPGA?

The falling edge which caused the glitch:

What exactly are you scoping here?

Ch3&4 are at 5V, is there some current/voltage limiting device between
the pins and the FPGA?

Are ch3 and ch4 your quadrature encoder inputs?

What's ch1 looking at?

If that falling edge is an input than at ~30ns it's shouldn't be what's causing
the problem unless you've got _terrible_ ground problems.

Here is where things get weird. Depending on which pins are chosen, it
is possible that the glitches will go away when a copy is sent out an IO
port. An important additional clue was the fact that an adjacent pin to
the clock input, when changed from unconfigured (input) to output, even
if just a static logic level was output, caused the glitching to go
away. More on that later.

This shows your design is still susceptible to asynchronous inputs toggling.

Synchronise both(all) the inputs at the IO to the system clock then use those
to look for falling or rising edges for your counter