Re: Counter clocks on both edges sometimes, but not when different IO pin is used

In this case, the solution is not to clock anything with your muxed
'clocks' since there is nothing that actually needs to be clocked with
those signals. Instead you should mux those input 'clocks' to create
a logic signal that you then synchronize to your FPGA's clock

I would probably take it a step further and synchronise the two 'clocks' to
the FPGA clock at the IO then select which of the two synchronised inputs is
used as the enable for the counter.

Generalising....

Mr CRC, FPGAs and the tools are designed to guarantee that the output of
one register clocked with one clock will get to the input of any other
register clocked with the same clock (as long as the build meets timing).
This is the beauty of the devices, you don't need to worry about timing,
just functionality.

Once you start introducing asynchronous clock transfers guaranteeing what happens
between them is difficult to constrain, and for the tools to analyse. This is
what needs to be carefully handled in your design.

It is easiest to design, constrain, guarantee meeting timing and so get
guaranteed functional devices if you keep the number of clocks to a minimum.

Preferably 1 (though this is rarely possible).



Nial.


.

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