Re: Bidirectional Bus

On Sep 9, 8:37 pm, nobody <cydrollin...@xxxxxxxxx> wrote:
On Sep 9, 10:03 am, "Antti.Luk...@xxxxxxxxxxxxxx"



<antti.luk...@xxxxxxxxxxxxxx> wrote:
On Sep 9, 6:28 pm, nobody <cydrollin...@xxxxxxxxx> wrote:

On Sep 8, 10:07 pm, "Antti.Luk...@xxxxxxxxxxxxxx"

<antti.luk...@xxxxxxxxxxxxxx> wrote:
On Sep 9, 1:58 am, nobody <cydrollin...@xxxxxxxxx> wrote:

Antti

Thanks Antti,

Ive tried that.

Cy drollinger

and? problem solved or not?

Antti

Antti,

No, That has the same effect as the current VDHL Bidirectional bus
attempt. The FPGA is being programmed but the bus does not release. It
releases when the CPLD is reprogrammed via JTAG, this is not an
option. I am not to familiar with driving a common trace between two
programmable chips and maybe missing something conceptually. I have
been just reading examples of bidirectional buses and have used a
couple different solutions, which are quite similar. All have the same
effect not releasing after the slave parallel programming of the FPGA
is complete. I might not be explaining the problem thoroughly. Well,
back at it. I will let you know when I get the problem solved.

Cy Drollinger

connect done to JUMPER
bus to free IO
test

the code works, so if you dont see bus released problem is somewhere
else

Antti

Antti,

What about the synthesis tool not actually handling the the VHDL
statement:

the_bus <= "ZZZZZZZZ" when FPGA_done ='1' else bus_reg;

in the appropriate way. I asked a question about setting a pullup on a
few of the Switch pins of the CPLD and I learned that using a pullup
on one of the pin in the XC2C64A causes all pins to in a pullup state.
After talking with another individual their maybe some primitives that
need to be instantiated in order for the the high Z bus to be
implemented?
I know the CPLD programs the FPGA I know the FPGA_done pin goes high,
100 ns, I know the FPGA can drive the LEDs through the CPLD and the
pins that programmed the FPGA, but not immediately after the CPLD
programs the FPGA. The CPLD must be reprogrammed through the JTAG
leading me to believe there is something wrong with the above VHDL
statement either in timing, something hangs, or the synthesis tool is
not performing what I think I am asking it to do, Go to a high Z state
after the FPGA is programmed.

Antti, Thank you for taking time to give solutions and time thinking
about my problem, it is appreciated.

Cy Drollinger


the_bus <= "ZZZZZZZZ" when FPGA_done ='1' else bus_reg;

this WILL RELEASE the pins.
even Xilinx tools cant be that bad to fail on this.

if this is what you have, and FPGA_done IS 1
then bus is tristated as well

if not take a break.
it helps

if you think the synthesis tools fail, DO AS I TOLD YOU
make the "Z" on spare pins of the CPLD and check with multimeter and
finger

what you are doing is SO simple.. its hard todo it wrong...

Antti








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