Re: Choice of Language for FPGA programming

On 4 Sep., 09:19, "HT-Lab" <han...@xxxxxxxxxx> wrote:
"glen herrmannsfeldt" <g...@xxxxxxxxxxxxxxxx> wrote in message

news:h7p82b$mgn$1@xxxxxxxxxxxxxxxxxxx



Andy <jonesa...@xxxxxxxxxxx> wrote:
(snip on verilog and VHDL)

< (Other than my personal bias) : Given the differences between coding
< for SW and coding for HW, VHDL is better at keeping a new user from
< making some ignorant mistakes. A new designer with a SW background is
< more likely to make typical "SW" mistakes in a language that looks
< more like the SW he is used to. Sometimes keeping the syntax apart
< helps in this regard. On the other hand, if one's SW background is in
< ada, you could make exactly the same argument in favor of verilog ;^)

I don't agree, but I believe it could be personal preference.
For one, I did some logic design with TTL gates before learning
verilog, so I know how to think in terms of logic.

Verilog isn't really that much like C.  There are people using
C as an HDL, and I completely agree that is a bad idea.

Don't be too quick to dismiss C for HDL, there are lots of companies that
develop algorithms in Matlab/C/C++/SC and then pass it on to a poor engineer to
"quickly" translate into VHDL/Verilog. Then a month later they require the same
algorithm but 5 times faster or with a "subtle change" which normally results
(requires) a costly redesign. For those applications you really want to use an
untimed language like C/C++ and use a tool (CatapultC/BlueSpec/
Forte/Synfora/etc...) to do all the design exploration (resource mapping/adding
pipelines/concurrency/etc) for you.

Given the progress these tools are making (most can now also handle control path
as well) and the amount of money companies like Intel/AMD are pouring into
sequential to concurrent research I wouldn't be surprise if the future of RTL is
neither VHDL nor Verilog.....

There are very good reasons to use imperative languages for rapid
prototyping and
synthesizing complex algorithms to hardware.
BUT:
We in the world would anyone want to use a language with as many side
effects
as C (or even worse C++) for that purpose????? If you like C syntax
that much use Java or C#-.
Siemens was doing Java to netlist before the System-C hype but they
were approached
with stupid arguments like "the AWT is sooo slow" which is completely
irrelevant as
for hardware prototyping one uses none of the APIs that usually come
with the language
and also does not use the garbage collector.
IIRC C does not even have a formal memory model, how is one supposed
to do
formal verification on C code?

Kolja
.

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