Re: Operating the Spartan 3A FPGA at maximum speed (320 MHz)

On Aug 24, 11:49 am, "Antti.Luk...@xxxxxxxxxxxxxx"
<antti.luk...@xxxxxxxxxxxxxx> wrote:
On Aug 24, 9:40 am, Sharath Raju <brshar...@xxxxxxxxx> wrote:



Hello,

Our project is to build a spectrometer, in which the FPGA is
configured to perform autocorrelation.
See:http://brsharath.googlepages.com/autocorr.jpegtoget an idea.
(The difference in our project is the two signals from antenna 1 and 2
acome from the same antenna). The basic building block is a Delay-
Multiply-Accumalate (DMAC) element. DMACs are aranged in a serial
manner to perform n-channel autocorrelation. All the DMACs share a
common clock.

In terms of hardware requirement, the input digital data should be
available to all the DMACs including the “farthest DMAC”. I am using
Spartan 3A FPGA (XC3S400A) which can be clocked at a maximum of 320
MHz, and there is a provision of providing external clock.

My question is :
1. Can the FPGA be easily clocked at 320 MHz using an external
oscillator ? or
Will I have to deal with serious “data synchronization” issues since
the signal is routed to the farthest DMAC ? If so, are there any
methods to overcome the problem ?

Thanks,
Sharath

very short: the design as in the picture will NOT work in S3a at 320
mhz clock.
give up..! that is look for other solution
Why ? Is it due to data synchronization or is it some other issue ? Please explain.

other solution 1
you clock at 160mhz using DDR in the IOB, and build the datapath 2
times in parallel
and double the data rate at the output IOBs again

this would reduce the internal clock to 160mhz, what may be ok already

Why do you think that clocking at 160MHz is safe ? I shall check whether the above solution is suitable for our application. Thanks!

Antti

.

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