Re: How do you handle build variants in VHDL?
- From: Mark McDougall <markm@xxxxxxxxx>
- Date: Fri, 24 Jul 2009 11:18:12 +1000
Mike Treseler wrote:
I agree. If some of my "switched off" code does not elaborate,
that means I have changed or eliminated the target of some identifier
that previously make the code usable.
I would either fix up the option or take it all out.
I have a project suite that I've been attempting to perfect for some time.
It consists of a "framework" if you like, comprising a hierarchy of
entities, some of which may be substituted with project-specific variants,
whilst others may be provided by generic, cross-project architectures. The
suite itself is used in "many" projects, each of which may be targeted to
"many" hardware platforms.
I use records as far as possible when defining the ports of entities
within the framework. Each entity can have up to a dozen records as ports,
as each record contains only closely-related signals.
In general thus far, record declarations are "global" across projects -
they never change. Recently however, I've introduced a record that may be
defined on a per-project basis. This record is used in a number of
entities throughout the suite. This doesn't cause problems with entity
ports so much - it's when, for example, those (variable) record members
are accessed directly in "generic" modules within the framework.
Now, this is all very much WIP, and I'm not claiming that the problem
can't better be solved (I've tried to use configurations but either they
just don't seem to suit my purpose, result in redundant coding effort
which complicates maintenance, or I can't work out how to use them
properly), but it is in these cases that it would be very useful to be
able to exclude code segments, based on a constant or generic or compiler
directive, that wouldn't - for this project - pass compilation.
And again, this is only one example.
Anyway, I offer this explanation not for any justification of my methods,
but merely an explanation of what I am trying to achieve. I would
acknowledge that this is far from the typical or perhaps even intended use
of VHDL.
Regardless, I'm not convinced that my goal is ultimately realisable using
current VHDL standards and current-gen tools (happy to be proven wrong).
What I _do_ know is that I could easily achieve this in software.
Regards,
--
Mark McDougall, Engineer
Virtual Logic Pty Ltd, <http://www.vl.com.au>
21-25 King St, Rockdale, 2216
Ph: +612-9599-3255 Fax: +612-9599-3266
.
- References:
- How do you handle build variants in VHDL?
- From: Mike Harrison
- Re: How do you handle build variants in VHDL?
- From: rickman
- Re: How do you handle build variants in VHDL?
- From: Mike Treseler
- Re: How do you handle build variants in VHDL?
- From: Mark McDougall
- Re: How do you handle build variants in VHDL?
- From: KJ
- Re: How do you handle build variants in VHDL?
- From: Mike Treseler
- How do you handle build variants in VHDL?
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