Re: Strange FPGA behavior

On Mon, 20 Jul 2009 11:36:00 -0700 (PDT), luudee wrote:

Sounds like a timing problem. Intermediate failures are usually
timing related.

Absolutely.

Where is the clock coming from, the DSP ? Do you cancel out the
clock buffer delay before you use it for the LED register ?

Painful recollections of a recent customer project which
had a clocked external interface - nothing too fast,
about 40MHz or so - output from FPGA, fed into the
streaming data interface of some microcontroller.
Something hard-to-fathom was going wrong. We
scratched heads, fooled around with timing
constraints in a desperate effort to get the clock
edges (at the FPGA registers) exactly lined up with
the centre of the data window. Static timing analysis
and oscilloscope measurements both said we had it
just right.... and the nearer we got to "just right",
the less reliable the data transfer. Angry project
managers, much consumption of coffee and discussion.

Finally I gave up in disgust and - after a struggle -
got a copy of the microcontroller software from the
programmer folk. The micro's interface control registers
had been set up for falling-edge clocking of the
interface, but all the specifications said rising-edge.
So the closer I got to centre-aligning the clock rise
in the data window, the worse the timing became!

Just one bit wrong in one *&&^% control register.
Just because one programmer couldn't read a spec.
Grrr.
--
Jonathan Bromley, Consultant

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