Re: How do you handle build variants in VHDL?
- From: rickman <gnuarm@xxxxxxxxx>
- Date: Mon, 20 Jul 2009 18:22:02 -0700 (PDT)
On Jul 20, 4:51 am, Mike Harrison <m...@xxxxxxxxxxxxxxx> wrote:
I'm doing a project in Lattice ISPLever ( which bears uncanny similarities to Xilinx ISE), which may
end up having several product variants, and was wondering how people typically handle compile-time
build variants for different product functionalities?
The sort of thing that if it was C software, you'd do it easily with #includes, #defines and
#ifdefs, but for reasons I can't understand, VHDL doesn't have anything like these simple
preprocessor functions.
Although HDLs are very different from programming languages, a preprocessor would be equally useful
& it seems ridiculous that nobody thought to include one in the standard.
Is there a simple way to 'add' a C style preprocessor to the build process?
You should also look up GENERATE. That is how to do actual code
"defines". GENERICS only get you parameters.
Rick
.
- Follow-Ups:
- Re: How do you handle build variants in VHDL?
- From: Mike Treseler
- Re: How do you handle build variants in VHDL?
- From: rickman
- Re: How do you handle build variants in VHDL?
- References:
- How do you handle build variants in VHDL?
- From: Mike Harrison
- How do you handle build variants in VHDL?
- Prev by Date: Re: How do you handle build variants in VHDL?
- Next by Date: Re: Xilinx WebPack 10.1 ISIM under Linux ?
- Previous by thread: Re: How do you handle build variants in VHDL?
- Next by thread: Re: How do you handle build variants in VHDL?
- Index(es):
Relevant Pages
|
