Re: Generating a negated clock

MM wrote:

"Nemesis" <nemesis@xxxxxxxxxxxxxxx> wrote in message
news:20090716184149.3460.49994.XPN@xxxxxxxxxxxxxxxx

I interfaced my DSP code with base code of the board (an ADC board).
I don't want to modify the original code. I think they didn't use the
Xilinx core because the fifo's depth is about 12000, Xilinx core accept
only power of 2 depths if I remember well.

I am pretty sure it would be easier and an overall better solution to
replace a weird FIFO than to create a weird clocking scheme. The reason they
didn't use a Xilinx core could be because they wanted the code to be
portable between different FPGA vendors (they might have ADC boards with
different FPGAs available), which is still a bad excuse for requiring 2
phases of the same clock.

In any case I doubt there's much value in their ADC interface code. You
could probably interface to the ADC directly yourself.

At the end they use (smaller) Xilinx Fifo core to build the large one, I
suppose they didn't use directly a 16k fifo core not to waste BRAMs.

Anyway I don't want to play with their implementation because it contains
also interface code for getting data from the FIFO on the PCI bus or
another customized bus.

Unfortunately I don't have the time to study their solution and modify it
in a reliable way.
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