Re: How to implementa an FSM in block ram

Hal Murray <hal-usenet@xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx> wrote:
(snip)

< Could you please say a bit more? How does data get corrupted when
< write-enable is off?

< I can understand a write going to the wrong place(s) if the address
< doesn't meet setup, but I don't see how metastability on the
< addresses can write somewhere when write-enable is off.

I suppose it makes some sense. The address decoders go to
enable lines that enable the signal coming out of the bit
cells onto the sense lines. If, for example, two enable lines
were active at once then two cells would be enabled onto the
same sense line. If the address goes metastable, it seems
that could happen. Presumably this is true for non-FPGA RAMs, too.

< I guess the actual implementation doesn't translate into normal logic
< where an off signal on write-enable would block the update
< signal even if wome other input to the gate was garbage.

-- glen
.

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